   1              		.cpu cortex-m4
   2              		.eabi_attribute 27, 1
   3              		.eabi_attribute 28, 1
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 6
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"gpio.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.align	1
  18              		.syntax unified
  19              		.thumb
  20              		.thumb_func
  21              		.fpu fpv4-sp-d16
  23              	NVIC_EnableIRQ:
  24              	.LFB108:
  25              		.file 1 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH04-GPIO\\
   1:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**************************************************************************//**
   2:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @file     core_cm4.h
   3:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
   4:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @version  V4.30
   5:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @date     20. October 2015
   6:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
   7:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
   8:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
   9:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    All rights reserved.
  10:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    Redistribution and use in source and binary forms, with or without
  11:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    modification, are permitted provided that the following conditions are met:
  12:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    - Redistributions of source code must retain the above copyright
  13:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      notice, this list of conditions and the following disclaimer.
  14:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    - Redistributions in binary form must reproduce the above copyright
  15:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      notice, this list of conditions and the following disclaimer in the
  16:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      documentation and/or other materials provided with the distribution.
  17:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    - Neither the name of ARM nor the names of its contributors may be used
  18:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      to endorse or promote products derived from this software without
  19:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      specific prior written permission.
  20:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    *
  21:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  25:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    POSSIBILITY OF SUCH DAMAGE.
  32:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    ---------------------------------------------------------------------------*/
  33:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  34:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  35:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if   defined ( __ICCARM__ )
  36:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  #pragma system_include         /* treat file as system include file for MISRA check */
  37:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  38:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #pragma clang system_header   /* treat file as system include file */
  39:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
  40:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  41:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
  42:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORE_CM4_H_GENERIC
  43:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  44:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include <stdint.h>
  45:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  46:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
  47:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  extern "C" {
  48:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
  49:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  50:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
  51:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  52:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   CMSIS violates the following MISRA-C:2004 rules:
  53:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  54:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  55:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      Function definitions in header files are used to allow 'inlining'.
  56:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  57:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  58:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      Unions are used for effective representation of core registers.
  59:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  60:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  61:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      Function-like macros are used to allow more efficient code.
  62:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
  63:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  64:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  65:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
  66:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  *                 CMSIS definitions
  67:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
  68:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
  69:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup Cortex_M4
  70:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
  71:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
  72:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  73:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*  CMSIS CM4 definitions */
  74:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS H
  75:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS H
  76:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
  77:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****                                     __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL versi
  78:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  79:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core *
  80:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  81:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  82:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if   defined ( __CC_ARM )
  83:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
  84:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
  85:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static __inline
  86:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  87:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  88:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
  89:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
  90:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static __inline
  91:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  92:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __GNUC__ )
  93:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for GNU Comp
  94:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for GNU C
  95:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
  96:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  97:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __ICCARM__ )
  98:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for IAR Comp
  99:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for IAR C
 100:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 101:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 102:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TMS470__ )
 103:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TI CCS C
 104:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 105:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 106:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TASKING__ )
 107:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TASKING 
 108:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for TASKI
 109:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 110:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 111:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __CSMC__ )
 112:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __packed
 113:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Co
 114:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                    /*!< inline keyword for COSMIC
 115:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 116:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 117:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #else
 118:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #error Unknown compiler
 119:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 120:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 121:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
 122:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
 123:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
 124:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if defined ( __CC_ARM )
 125:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __TARGET_FPU_VFP
 126:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 127:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 128:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 129:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 130:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 131:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 132:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 133:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 134:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 135:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 136:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
 137:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __ARM_PCS_VFP
 138:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1)
 139:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 140:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 141:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
 142:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 143:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 144:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 145:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 146:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 147:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 148:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __GNUC__ )
 149:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
 150:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 151:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 152:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 153:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 154:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 155:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 156:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 157:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 158:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 159:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 160:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __ICCARM__ )
 161:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __ARMVFP__
 162:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 163:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 164:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 165:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 166:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 167:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 168:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 169:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 170:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 171:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 172:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TMS470__ )
 173:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __TI_VFP_SUPPORT__
 174:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 175:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 176:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 177:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 178:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 179:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 180:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 181:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 182:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 183:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 184:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TASKING__ )
 185:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __FPU_VFP__
 186:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 187:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 188:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 189:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 190:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 191:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 192:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 193:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 194:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 195:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 196:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __CSMC__ )
 197:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if ( __CSMC__ & 0x400U)
 198:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 199:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 200:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 201:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 202:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 203:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 204:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 205:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 206:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 207:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 208:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 209:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 210:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmInstr.h"                /* Core Instruction Access */
 211:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmFunc.h"                 /* Core Function Access */
 212:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
 213:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 214:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 215:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
 216:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 217:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 218:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
 219:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 220:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CMSIS_GENERIC
 221:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 222:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
 223:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
 224:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 225:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 226:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  extern "C" {
 227:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 228:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 229:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* check device defines and use defaults */
 230:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
 231:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __CM4_REV
 232:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __CM4_REV               0x0000U
 233:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__CM4_REV not defined in device header file; using default!"
 234:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 235:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 236:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __FPU_PRESENT
 237:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_PRESENT             0U
 238:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
 239:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 240:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 241:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __MPU_PRESENT
 242:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __MPU_PRESENT             0U
 243:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
 244:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 245:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 246:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __NVIC_PRIO_BITS
 247:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __NVIC_PRIO_BITS          4U
 248:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 249:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 250:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 251:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __Vendor_SysTickConfig
 252:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __Vendor_SysTickConfig    0U
 253:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 254:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 255:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 256:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 257:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
 258:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 259:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 260:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 261:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     <strong>IO Type Qualifiers</strong> are used
 262:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     \li to specify the access to peripheral variables.
 263:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     \li for automatic generation of peripheral register debug information.
 264:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
 265:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 266:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 267:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #else
 268:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 269:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 270:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 271:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 272:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 273:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* following defines should be used for structure members */
 274:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 275:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 276:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 277:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 278:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group Cortex_M4 */
 279:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 280:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 281:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 282:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
 283:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  *                 Register Abstraction
 284:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   Core Register contain:
 285:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Register
 286:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core NVIC Register
 287:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SCB Register
 288:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SysTick Register
 289:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Debug Register
 290:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core MPU Register
 291:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core FPU Register
 292:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
 293:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 294:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 295:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 296:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
 297:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 298:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 299:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
 300:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 301:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Core Register type definitions.
 302:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 303:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 304:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 305:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 306:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 307:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 308:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 309:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 310:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 311:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 312:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
 313:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 314:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
 315:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 316:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 317:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 318:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 319:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 320:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 321:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 322:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } APSR_Type;
 323:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 324:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* APSR Register Definitions */
 325:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 326:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 327:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 328:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 329:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 330:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 331:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 332:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 333:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 334:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 335:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 336:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 337:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
 338:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
 339:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 340:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
 341:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
 342:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 343:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 344:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 345:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 346:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 347:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 348:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 349:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 350:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 351:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 352:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 353:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 354:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 355:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } IPSR_Type;
 356:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 357:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* IPSR Register Definitions */
 358:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 359:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 360:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 361:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 362:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 363:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 364:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 365:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 366:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 367:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 368:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 369:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 370:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
 371:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 372:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
 373:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 374:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
 375:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 376:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 377:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 378:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 379:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 380:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 381:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 382:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } xPSR_Type;
 383:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 384:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* xPSR Register Definitions */
 385:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 386:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 387:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 388:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 389:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 390:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 391:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 392:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 393:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 394:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 395:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 396:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 397:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
 398:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
 399:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 400:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_IT_Pos                        25U                                            /*!< xPSR
 401:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR
 402:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 403:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 404:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 405:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 406:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
 407:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
 408:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 409:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 410:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 411:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 412:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 413:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 414:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Control Registers (CONTROL).
 415:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 416:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 417:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 418:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 419:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 420:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
 421:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 422:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
 423:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
 424:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 425:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 426:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } CONTROL_Type;
 427:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 428:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* CONTROL Register Definitions */
 429:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
 430:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
 431:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 432:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 433:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 434:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 435:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
 436:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
 437:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 438:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_CORE */
 439:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 440:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 441:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 442:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
 443:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 444:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Type definitions for the NVIC Registers
 445:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 446:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 447:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 448:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 449:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 450:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 451:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 452:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 453:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 454:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[24U];
 455:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 456:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RSERVED1[24U];
 457:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 458:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[24U];
 459:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 460:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[24U];
 461:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
 462:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[56U];
 463:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
 464:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[644U];
 465:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
 466:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }  NVIC_Type;
 467:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 468:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
 469:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
 470:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
 471:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 472:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_NVIC */
 473:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 474:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 475:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 476:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 477:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 478:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Control Block Registers
 479:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 480:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 481:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 482:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 483:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Control Block (SCB).
 484:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 485:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 486:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 487:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 488:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 489:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 490:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 491:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 492:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 493:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
 494:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 495:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
 496:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
 497:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
 498:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
 499:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
 500:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
 501:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
 502:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
 503:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
 504:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
 505:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
 506:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[5U];
 507:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
 508:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } SCB_Type;
 509:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 510:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB CPUID Register Definitions */
 511:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 512:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 513:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 514:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 515:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 516:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 517:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 518:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 519:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 520:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 521:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 522:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 523:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 524:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 525:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 526:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
 527:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 528:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 529:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 530:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 531:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 532:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 533:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 534:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 535:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 536:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 537:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 538:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 539:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 540:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 541:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 542:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 543:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 544:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 545:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 546:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 547:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 548:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 549:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 550:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 551:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
 552:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
 553:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 554:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 555:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 556:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 557:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
 558:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
 559:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
 560:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 561:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 562:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 563:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 564:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 565:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 566:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 567:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 568:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 569:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 570:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 571:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
 572:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
 573:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 574:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 575:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 576:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 577:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 578:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 579:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 580:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
 581:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
 582:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 583:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB System Control Register Definitions */
 584:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 585:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 586:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 587:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 588:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 589:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 590:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 591:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 592:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 593:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Configuration Control Register Definitions */
 594:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 595:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 596:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 597:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
 598:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
 599:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 600:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
 601:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
 602:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 603:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 604:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 605:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 606:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
 607:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
 608:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 609:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
 610:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
 611:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 612:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
 613:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
 614:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
 615:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 616:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
 617:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
 618:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 619:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
 620:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
 621:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 622:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 623:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 624:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 625:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
 626:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
 627:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 628:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
 629:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
 630:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 631:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
 632:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
 633:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 634:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
 635:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
 636:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 637:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
 638:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
 639:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 640:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
 641:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
 642:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 643:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
 644:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
 645:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 646:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
 647:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
 648:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 649:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
 650:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
 651:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 652:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
 653:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
 654:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 655:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
 656:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
 657:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
 658:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 659:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
 660:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
 661:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 662:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
 663:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
 664:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 665:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
 666:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
 667:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
 668:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 669:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
 670:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
 671:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 672:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
 673:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
 674:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 675:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
 676:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
 677:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
 678:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 679:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
 680:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
 681:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 682:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
 683:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
 684:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 685:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
 686:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
 687:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 688:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
 689:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
 690:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 691:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SCB */
 692:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 693:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 694:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 695:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 696:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
 697:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
 698:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 699:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 700:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 701:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 702:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
 703:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 704:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 705:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 706:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
 707:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
 708:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 709:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } SCnSCB_Type;
 710:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 711:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Interrupt Controller Type Register Definitions */
 712:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
 713:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
 714:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 715:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Auxiliary Control Register Definitions */
 716:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: 
 717:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: 
 718:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 719:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: 
 720:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: 
 721:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 722:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
 723:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
 724:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 725:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
 726:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
 727:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 728:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
 729:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
 730:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 731:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
 732:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 733:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 734:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 735:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 736:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 737:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Timer Registers.
 738:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 739:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 740:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 741:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 742:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Timer (SysTick).
 743:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 744:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 745:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 746:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 747:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 748:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 749:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 750:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } SysTick_Type;
 751:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 752:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Control / Status Register Definitions */
 753:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 754:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 755:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 756:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 757:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 758:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 759:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 760:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 761:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 762:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 763:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 764:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 765:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Reload Register Definitions */
 766:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 767:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 768:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 769:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Current Register Definitions */
 770:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 771:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 772:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 773:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Calibration Register Definitions */
 774:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 775:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 776:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 777:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 778:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 779:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 780:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 781:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 782:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 783:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SysTick */
 784:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 785:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 786:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 787:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 788:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
 789:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
 790:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 791:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 792:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 793:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 794:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 795:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 796:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 797:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 798:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  union
 799:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 800:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
 801:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
 802:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
 803:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
 804:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[864U];
 805:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
 806:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[15U];
 807:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
 808:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[15U];
 809:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
 810:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[29U];
 811:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
 812:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
 813:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
 814:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[43U];
 815:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
 816:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
 817:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[6U];
 818:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
 819:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
 820:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
 821:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
 822:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
 823:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
 824:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
 825:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
 826:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
 827:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
 828:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
 829:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
 830:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } ITM_Type;
 831:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 832:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Trace Privilege Register Definitions */
 833:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
 834:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM 
 835:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 836:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Trace Control Register Definitions */
 837:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
 838:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
 839:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 840:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
 841:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
 842:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 843:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
 844:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
 845:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 846:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
 847:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
 848:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 849:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
 850:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
 851:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 852:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
 853:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
 854:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 855:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
 856:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
 857:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 858:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
 859:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
 860:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 861:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
 862:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
 863:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 864:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Write Register Definitions */
 865:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
 866:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
 867:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 868:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Read Register Definitions */
 869:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
 870:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
 871:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 872:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Mode Control Register Definitions */
 873:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
 874:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
 875:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 876:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Lock Status Register Definitions */
 877:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
 878:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
 879:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 880:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
 881:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
 882:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 883:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
 884:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
 885:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 886:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
 887:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 888:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 889:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 890:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 891:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
 892:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
 893:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 894:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 895:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 896:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 897:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 898:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 899:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 900:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 901:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
 902:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
 903:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
 904:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
 905:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
 906:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
 907:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
 908:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
 909:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
 910:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
 911:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
 912:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
 913:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
 914:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
 915:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
 916:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[1U];
 917:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
 918:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
 919:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
 920:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[1U];
 921:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
 922:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
 923:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 924:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } DWT_Type;
 925:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 926:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Control Register Definitions */
 927:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
 928:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
 929:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 930:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
 931:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
 932:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 933:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
 934:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
 935:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 936:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
 937:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
 938:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 939:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
 940:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
 941:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 942:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
 943:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
 944:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 945:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
 946:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
 947:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 948:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
 949:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
 950:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 951:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
 952:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
 953:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 954:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
 955:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
 956:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 957:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
 958:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
 959:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 960:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
 961:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
 962:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 963:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
 964:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
 965:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 966:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
 967:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
 968:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 969:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
 970:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
 971:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 972:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
 973:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
 974:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 975:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
 976:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
 977:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 978:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
 979:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
 980:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 981:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT CPI Count Register Definitions */
 982:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
 983:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
 984:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 985:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
 986:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
 987:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
 988:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 989:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Sleep Count Register Definitions */
 990:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
 991:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
 992:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 993:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT LSU Count Register Definitions */
 994:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
 995:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
 996:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 997:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
 998:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
 999:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
1000:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1001:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Comparator Mask Register Definitions */
1002:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
1003:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
1004:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1005:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Comparator Function Register Definitions */
1006:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
1007:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
1008:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1009:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
1010:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
1011:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1012:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
1013:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
1014:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1015:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
1016:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
1017:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1018:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
1019:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
1020:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1021:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
1022:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
1023:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1024:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
1025:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
1026:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1027:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
1028:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
1029:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1030:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
1031:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
1032:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1033:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
1034:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1035:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1036:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1037:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1038:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
1039:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
1040:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1041:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1042:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1043:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1044:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
1045:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1046:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1047:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1048:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
1049:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
1050:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[2U];
1051:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
1052:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[55U];
1053:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
1054:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[131U];
1055:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
1056:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
1057:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
1058:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[759U];
1059:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
1060:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
1061:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
1062:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[1U];
1063:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
1064:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
1065:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
1066:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[39U];
1067:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
1068:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
1069:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED7[8U];
1070:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
1071:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
1072:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } TPI_Type;
1073:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1074:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
1075:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
1076:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
1077:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1078:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
1079:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
1080:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
1081:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1082:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
1083:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
1084:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
1085:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1086:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
1087:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
1088:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1089:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
1090:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
1091:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1092:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
1093:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
1094:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1095:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
1096:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
1097:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
1098:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1099:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
1100:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
1101:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1102:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI TRIGGER Register Definitions */
1103:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
1104:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
1105:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1106:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
1107:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1108:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
1109:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1110:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1111:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
1112:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1113:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1114:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
1115:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1116:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1117:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
1118:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1119:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
1120:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
1121:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1122:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
1123:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
1124:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1125:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
1126:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
1127:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1128:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
1129:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITA
1130:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITA
1131:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1132:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
1133:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1134:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
1135:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1136:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1137:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
1138:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1139:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1140:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
1141:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1142:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1143:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
1144:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1145:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
1146:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
1147:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1148:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
1149:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
1150:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1151:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
1152:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
1153:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1154:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
1155:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITA
1156:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITA
1157:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1158:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
1159:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
1160:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
1161:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1162:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI DEVID Register Definitions */
1163:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
1164:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
1165:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1166:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
1167:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
1168:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1169:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
1170:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
1171:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1172:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
1173:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
1174:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1175:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
1176:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
1177:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1178:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
1179:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
1180:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1181:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI DEVTYPE Register Definitions */
1182:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEV
1183:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
1184:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1185:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEV
1186:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
1187:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1188:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
1189:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1190:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1191:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__MPU_PRESENT == 1U)
1192:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1193:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1194:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
1195:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
1196:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1197:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1198:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1199:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1200:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
1201:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1202:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1203:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1204:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
1205:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
1206:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
1207:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
1208:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
1209:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
1210:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
1211:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
1212:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
1213:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
1214:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
1215:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } MPU_Type;
1216:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1217:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Type Register Definitions */
1218:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
1219:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
1220:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1221:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
1222:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
1223:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1224:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
1225:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
1226:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1227:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Control Register Definitions */
1228:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
1229:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
1230:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1231:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
1232:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
1233:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1234:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
1235:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
1236:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1237:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Number Register Definitions */
1238:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
1239:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
1240:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1241:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Base Address Register Definitions */
1242:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
1243:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
1244:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1245:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
1246:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
1247:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1248:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
1249:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
1250:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1251:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
1252:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
1253:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
1254:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1255:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
1256:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
1257:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1258:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
1259:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
1260:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1261:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
1262:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
1263:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1264:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
1265:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
1266:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1267:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
1268:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
1269:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1270:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
1271:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
1272:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1273:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
1274:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
1275:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1276:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
1277:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
1278:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1279:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
1280:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
1281:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1282:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_MPU */
1283:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1284:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1285:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1286:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__FPU_PRESENT == 1U)
1287:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1288:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1289:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
1290:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
1291:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1292:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1293:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1294:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1295:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
1296:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1297:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1298:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1299:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
1300:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
1301:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
1302:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
1303:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
1304:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
1305:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } FPU_Type;
1306:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1307:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Context Control Register Definitions */
1308:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
1309:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
1310:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1311:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
1312:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
1313:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1314:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
1315:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
1316:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1317:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
1318:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
1319:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1320:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
1321:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
1322:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1323:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
1324:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
1325:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1326:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
1327:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
1328:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1329:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
1330:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
1331:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1332:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
1333:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
1334:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1335:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Context Address Register Definitions */
1336:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
1337:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
1338:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1339:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
1340:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
1341:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
1342:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1343:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
1344:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
1345:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1346:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
1347:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
1348:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1349:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
1350:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
1351:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1352:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
1353:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
1354:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
1355:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1356:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
1357:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
1358:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1359:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
1360:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
1361:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1362:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
1363:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
1364:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1365:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
1366:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
1367:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1368:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
1369:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
1370:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1371:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
1372:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
1373:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1374:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
1375:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
1376:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1377:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
1378:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
1379:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
1380:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1381:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
1382:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
1383:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1384:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
1385:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
1386:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1387:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
1388:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
1389:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1390:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_FPU */
1391:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1392:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1393:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1394:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1395:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1396:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
1397:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Core Debug Registers
1398:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1399:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1400:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1401:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1402:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
1403:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1404:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1405:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1406:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
1407:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
1408:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
1409:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
1410:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } CoreDebug_Type;
1411:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1412:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
1413:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
1414:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
1415:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1416:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
1417:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
1418:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1419:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
1420:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
1421:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1422:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
1423:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
1424:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1425:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
1426:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
1427:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1428:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
1429:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
1430:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1431:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
1432:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
1433:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1434:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
1435:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
1436:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1437:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
1438:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
1439:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1440:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
1441:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
1442:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1443:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
1444:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
1445:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1446:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
1447:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
1448:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1449:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Core Register Selector Register Definitions */
1450:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
1451:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
1452:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1453:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
1454:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
1455:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1456:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
1457:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
1458:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
1459:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1460:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
1461:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
1462:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1463:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
1464:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
1465:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1466:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
1467:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
1468:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1469:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
1470:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
1471:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1472:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
1473:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
1474:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1475:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
1476:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
1477:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1478:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
1479:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
1480:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1481:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
1482:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
1483:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1484:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
1485:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
1486:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1487:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
1488:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
1489:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1490:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
1491:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
1492:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1493:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
1494:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
1495:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1496:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
1497:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1498:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1499:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1500:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
1501:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
1502:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1503:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1504:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1505:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1506:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1507:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
1508:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] field  Name of the register bit field.
1509:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] value  Value of the bit field.
1510:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \return           Masked and shifted value.
1511:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
1512:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
1513:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1514:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1515:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief     Mask and shift a register value to extract a bit filed value.
1516:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] field  Name of the register bit field.
1517:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] value  Value of register.
1518:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \return           Masked and shifted bit field value.
1519:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
1520:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
1521:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1522:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
1523:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1524:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1525:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1526:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
1527:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_core_base     Core Definitions
1528:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Definitions for base addresses, unions, and structures.
1529:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1530:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1531:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1532:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Memory mapping of Cortex-M4 Hardware */
1533:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
1534:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
1535:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
1536:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
1537:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
1538:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
1539:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
1540:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
1541:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1542:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
1543:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
1544:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
1545:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
1546:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
1547:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
1548:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
1549:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
1550:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1551:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__MPU_PRESENT == 1U)
1552:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
1553:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
1554:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1555:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1556:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__FPU_PRESENT == 1U)
1557:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
1558:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
1559:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1560:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1561:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} */
1562:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1563:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1564:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1565:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
1566:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  *                Hardware Abstraction Layer
1567:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   Core Function Interface contains:
1568:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core NVIC Functions
1569:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SysTick Functions
1570:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Debug Functions
1571:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Register Access Functions
1572:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
1573:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1574:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1575:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
1576:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1577:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1578:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1579:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ##########################   NVIC functions  #################################### */
1580:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1581:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
1582:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1583:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
1584:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1585:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1586:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1587:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1588:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Set Priority Grouping
1589:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Sets the priority grouping field using the required unlock sequence.
1590:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1591:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            Only values from 0..7 are used.
1592:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            In case of a conflict between priority grouping and available
1593:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1594:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      PriorityGroup  Priority grouping field.
1595:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1596:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1597:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1598:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t reg_value;
1599:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
1600:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1601:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
1602:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
1603:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value  =  (reg_value                                   |
1604:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1605:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****                 (PriorityGroupTmp << 8U)                      );              /* Insert write key a
1606:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   SCB->AIRCR =  reg_value;
1607:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
1608:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1609:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1610:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1611:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Get Priority Grouping
1612:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
1613:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1614:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1615:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1616:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1617:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1618:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
1619:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1620:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1621:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1622:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Enable External Interrupt
1623:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Enables a device-specific interrupt in the NVIC interrupt controller.
1624:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
1625:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1626:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1627:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
  26              		.loc 1 1627 0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 8
  29              		@ frame_needed = 1, uses_anonymous_args = 0
  30              		@ link register save eliminated.
  31 0000 80B4     		push	{r7}
  32              		.cfi_def_cfa_offset 4
  33              		.cfi_offset 7, -4
  34 0002 83B0     		sub	sp, sp, #12
  35              		.cfi_def_cfa_offset 16
  36 0004 00AF     		add	r7, sp, #0
  37              		.cfi_def_cfa_register 7
  38 0006 0346     		mov	r3, r0
  39 0008 FB71     		strb	r3, [r7, #7]
1628:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
  40              		.loc 1 1628 0
  41 000a FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
  42 000c 03F01F02 		and	r2, r3, #31
  43 0010 0749     		ldr	r1, .L2
  44 0012 97F90730 		ldrsb	r3, [r7, #7]
  45 0016 5B09     		lsrs	r3, r3, #5
  46 0018 0120     		movs	r0, #1
  47 001a 00FA02F2 		lsl	r2, r0, r2
  48 001e 41F82320 		str	r2, [r1, r3, lsl #2]
1629:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
  49              		.loc 1 1629 0
  50 0022 00BF     		nop
  51 0024 0C37     		adds	r7, r7, #12
  52              		.cfi_def_cfa_offset 4
  53 0026 BD46     		mov	sp, r7
  54              		.cfi_def_cfa_register 13
  55              		@ sp needed
  56 0028 5DF8047B 		ldr	r7, [sp], #4
  57              		.cfi_restore 7
  58              		.cfi_def_cfa_offset 0
  59 002c 7047     		bx	lr
  60              	.L3:
  61 002e 00BF     		.align	2
  62              	.L2:
  63 0030 00E100E0 		.word	-536813312
  64              		.cfi_endproc
  65              	.LFE108:
  67              		.align	1
  68              		.syntax unified
  69              		.thumb
  70              		.thumb_func
  71              		.fpu fpv4-sp-d16
  73              	NVIC_DisableIRQ:
  74              	.LFB109:
1630:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1631:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1632:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1633:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Disable External Interrupt
1634:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Disables a device-specific interrupt in the NVIC interrupt controller.
1635:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
1636:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1637:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1638:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
  75              		.loc 1 1638 0
  76              		.cfi_startproc
  77              		@ args = 0, pretend = 0, frame = 8
  78              		@ frame_needed = 1, uses_anonymous_args = 0
  79              		@ link register save eliminated.
  80 0034 80B4     		push	{r7}
  81              		.cfi_def_cfa_offset 4
  82              		.cfi_offset 7, -4
  83 0036 83B0     		sub	sp, sp, #12
  84              		.cfi_def_cfa_offset 16
  85 0038 00AF     		add	r7, sp, #0
  86              		.cfi_def_cfa_register 7
  87 003a 0346     		mov	r3, r0
  88 003c FB71     		strb	r3, [r7, #7]
1639:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
  89              		.loc 1 1639 0
  90 003e FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
  91 0040 03F01F02 		and	r2, r3, #31
  92 0044 0749     		ldr	r1, .L5
  93 0046 97F90730 		ldrsb	r3, [r7, #7]
  94 004a 5B09     		lsrs	r3, r3, #5
  95 004c 0120     		movs	r0, #1
  96 004e 00FA02F2 		lsl	r2, r0, r2
  97 0052 2033     		adds	r3, r3, #32
  98 0054 41F82320 		str	r2, [r1, r3, lsl #2]
1640:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
  99              		.loc 1 1640 0
 100 0058 00BF     		nop
 101 005a 0C37     		adds	r7, r7, #12
 102              		.cfi_def_cfa_offset 4
 103 005c BD46     		mov	sp, r7
 104              		.cfi_def_cfa_register 13
 105              		@ sp needed
 106 005e 5DF8047B 		ldr	r7, [sp], #4
 107              		.cfi_restore 7
 108              		.cfi_def_cfa_offset 0
 109 0062 7047     		bx	lr
 110              	.L6:
 111              		.align	2
 112              	.L5:
 113 0064 00E100E0 		.word	-536813312
 114              		.cfi_endproc
 115              	.LFE109:
 117              		.global	GPIO_ODD_ARR
 118              		.data
 119              		.align	2
 122              	GPIO_ODD_ARR:
 123 0000 004C0040 		.word	1073761280
 124 0004 204C0040 		.word	1073761312
 125 0008 404C0040 		.word	1073761344
 126 000c 604C0040 		.word	1073761376
 127 0010 804C0040 		.word	1073761408
 128              		.global	GPIO_EVEN_ARR
 129              		.align	2
 132              	GPIO_EVEN_ARR:
 133 0014 004C0040 		.word	1073761280
 134 0018 204C0040 		.word	1073761312
 135 001c 404C0040 		.word	1073761344
 136 0020 604C0040 		.word	1073761376
 137 0024 804C0040 		.word	1073761408
 138              		.text
 139              		.align	1
 140              		.syntax unified
 141              		.thumb
 142              		.thumb_func
 143              		.fpu fpv4-sp-d16
 145              	gpio_port_pin_resolution:
 146              	.LFB123:
 147              		.file 2 "srcc/gpio.c"
   1:srcc/gpio.c   **** //===========================================================================
   2:srcc/gpio.c   **** //ÎÄ¼þÃû³Æ£ºgpio.c
   3:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£ºGPIOµ×²ãÇý¶¯¹¹¼þÔ´ÎÄ¼þ
   4:srcc/gpio.c   **** //°æÈ¨ËùÓÐ£ºËÕÖÝ´óÑ§Ç¶ÈëÊ½ÖÐÐÄ(sumcu.suda.edu.cn)
   5:srcc/gpio.c   **** //¸üÐÂ¼ÇÂ¼£º2017-11-09  V1.0
   6:srcc/gpio.c   **** //===========================================================================
   7:srcc/gpio.c   **** #include "gpio.h"   //°üº¬±¾¹¹¼þÍ·ÎÄ¼þ
   8:srcc/gpio.c   **** 
   9:srcc/gpio.c   **** //¸÷¶Ë¿Ú»ùµØÖ··ÅÈë³£ÊýÊý¾Ý×éGPIO_ODD_ARRºÍGPIO_EVEN_ARRÖÐ ¸÷¶Ë¿Ú»ùµØÖ·¶¨ÒåÔÚmsp432p401r.hÎÄ¼þÖÐ
  10:srcc/gpio.c   ****  const DIO_PORT_Odd_Interruptable_Type* GPIO_ODD_ARR[]={P1,P3,P5,P7,P9};
  11:srcc/gpio.c   ****  const DIO_PORT_Even_Interruptable_Type* GPIO_EVEN_ARR[]={P2,P4,P6,P8,P10};
  12:srcc/gpio.c   **** 
  13:srcc/gpio.c   **** //----------------------ÒÔÏÂÎªÄÚ²¿º¯Êý´æ·Å´¦-------------------------------------
  14:srcc/gpio.c   **** //===========================================================================
  15:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_port_pin_resolution
  16:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
  17:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º¶Ë¿ÚºÅ|Òý½ÅºÅ(PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
  18:srcc/gpio.c   **** //         port£º¶Ë¿ÚºÅ
  19:srcc/gpio.c   **** //		   pin:Òý½ÅºÅ£¨0~16£¬Êµ¼ÊÈ¡ÖµÓÉÐ¾Æ¬µÄÎïÀíÒý½Å¾ö¶¨£©
  20:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£º½«´«½ø²ÎÊýport_pin½øÐÐ½âÎö£¬µÃ³ö¾ßÌå¶Ë¿ÚºÅÓëÒý½ÅºÅ (PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
  21:srcc/gpio.c   **** //         ½âÎöÎªPORT_2Óë0£¬²¢½«Æä·Ö±ð¸³Öµ¸øportÓëpin£©¡£
  22:srcc/gpio.c   **** //===========================================================================
  23:srcc/gpio.c   **** static void gpio_port_pin_resolution(uint16_t port_pin,uint8_t* port,uint8_t* pin)
  24:srcc/gpio.c   **** {
 148              		.loc 2 24 0
 149              		.cfi_startproc
 150              		@ args = 0, pretend = 0, frame = 16
 151              		@ frame_needed = 1, uses_anonymous_args = 0
 152              		@ link register save eliminated.
 153 0068 80B4     		push	{r7}
 154              		.cfi_def_cfa_offset 4
 155              		.cfi_offset 7, -4
 156 006a 85B0     		sub	sp, sp, #20
 157              		.cfi_def_cfa_offset 24
 158 006c 00AF     		add	r7, sp, #0
 159              		.cfi_def_cfa_register 7
 160 006e 0346     		mov	r3, r0
 161 0070 B960     		str	r1, [r7, #8]
 162 0072 7A60     		str	r2, [r7, #4]
 163 0074 FB81     		strh	r3, [r7, #14]	@ movhi
  25:srcc/gpio.c   **** 	*port = (port_pin>>8);
 164              		.loc 2 25 0
 165 0076 FB89     		ldrh	r3, [r7, #14]
 166 0078 1B0A     		lsrs	r3, r3, #8
 167 007a 9BB2     		uxth	r3, r3
 168 007c DAB2     		uxtb	r2, r3
 169 007e BB68     		ldr	r3, [r7, #8]
 170 0080 1A70     		strb	r2, [r3]
  26:srcc/gpio.c   **** 	*pin = port_pin;
 171              		.loc 2 26 0
 172 0082 FB89     		ldrh	r3, [r7, #14]	@ movhi
 173 0084 DAB2     		uxtb	r2, r3
 174 0086 7B68     		ldr	r3, [r7, #4]
 175 0088 1A70     		strb	r2, [r3]
  27:srcc/gpio.c   **** }
 176              		.loc 2 27 0
 177 008a 00BF     		nop
 178 008c 1437     		adds	r7, r7, #20
 179              		.cfi_def_cfa_offset 4
 180 008e BD46     		mov	sp, r7
 181              		.cfi_def_cfa_register 13
 182              		@ sp needed
 183 0090 5DF8047B 		ldr	r7, [sp], #4
 184              		.cfi_restore 7
 185              		.cfi_def_cfa_offset 0
 186 0094 7047     		bx	lr
 187              		.cfi_endproc
 188              	.LFE123:
 190              		.align	1
 191              		.global	gpio_init
 192              		.syntax unified
 193              		.thumb
 194              		.thumb_func
 195              		.fpu fpv4-sp-d16
 197              	gpio_init:
 198              	.LFB124:
  28:srcc/gpio.c   **** //----------------------------ÄÚ²¿º¯Êý½áÊø-------------------------------------
  29:srcc/gpio.c   **** //===========================================================================
  30:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_init
  31:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
  32:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º(¶Ë¿ÚºÅ)|(Òý½ÅºÅ)(PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
  33:srcc/gpio.c   **** //          dir£ºÒý½Å·½Ïò£¨0=ÊäÈë£¬1=Êä³ö,¿ÉÓÃÒý½Å·½Ïòºê¶¨Òå£©
  34:srcc/gpio.c   **** //          state£º¶Ë¿ÚÒý½Å³õÊ¼×´Ì¬£¨0=µÍµçÆ½£¬1=¸ßµçÆ½£©
  35:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£º³õÊ¼»¯Ö¸¶¨¶Ë¿ÚÒý½Å×÷ÎªGPIOÒý½Å¹¦ÄÜ£¬²¢¶¨ÒåÎªÊäÈë»òÊä³ö£¬ÈôÊÇÊä³ö£¬
  36:srcc/gpio.c   **** //          »¹Ö¸¶¨³õÊ¼×´Ì¬ÊÇµÍµçÆ½»ò¸ßµçÆ½
  37:srcc/gpio.c   **** //===========================================================================
  38:srcc/gpio.c   **** void gpio_init(uint16_t port_pin, uint8_t dir, uint8_t state)
  39:srcc/gpio.c   **** {
 199              		.loc 2 39 0
 200              		.cfi_startproc
 201              		@ args = 0, pretend = 0, frame = 24
 202              		@ frame_needed = 1, uses_anonymous_args = 0
 203 0096 80B5     		push	{r7, lr}
 204              		.cfi_def_cfa_offset 8
 205              		.cfi_offset 7, -8
 206              		.cfi_offset 14, -4
 207 0098 86B0     		sub	sp, sp, #24
 208              		.cfi_def_cfa_offset 32
 209 009a 00AF     		add	r7, sp, #0
 210              		.cfi_def_cfa_register 7
 211 009c 0346     		mov	r3, r0
 212 009e FB80     		strh	r3, [r7, #6]	@ movhi
 213 00a0 0B46     		mov	r3, r1
 214 00a2 7B71     		strb	r3, [r7, #5]
 215 00a4 1346     		mov	r3, r2
 216 00a6 3B71     		strb	r3, [r7, #4]
  40:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
  41:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
  42:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
  43:srcc/gpio.c   **** 	DIO_PORT_Not_Interruptable_Type* gpio_not_ptr;
  44:srcc/gpio.c   **** 	memset((void *)&gpio_even_ptr,0,sizeof(gpio_even_ptr));
 217              		.loc 2 44 0
 218 00a8 0023     		movs	r3, #0
 219 00aa FB60     		str	r3, [r7, #12]
  45:srcc/gpio.c   **** 	uint8_t port;
  46:srcc/gpio.c   **** 	uint8_t pin;
  47:srcc/gpio.c   **** 	//½âÎö¶Ë¿Ú»¹ÓÐÒý½Å
  48:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 220              		.loc 2 48 0
 221 00ac 07F10A02 		add	r2, r7, #10
 222 00b0 07F10B01 		add	r1, r7, #11
 223 00b4 FB88     		ldrh	r3, [r7, #6]
 224 00b6 1846     		mov	r0, r3
 225 00b8 FFF7D6FF 		bl	gpio_port_pin_resolution
  49:srcc/gpio.c   **** 	//ÅÐ¶ÏÊÇ·ñÎªJ¿Ú
  50:srcc/gpio.c   **** 	if(port >= 10)
 226              		.loc 2 50 0
 227 00bc FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 228 00be 092B     		cmp	r3, #9
 229 00c0 66D9     		bls	.L9
  51:srcc/gpio.c   **** 	{
  52:srcc/gpio.c   **** 		gpio_not_ptr = PJ;
 230              		.loc 2 52 0
 231 00c2 9C4B     		ldr	r3, .L24
 232 00c4 3B61     		str	r3, [r7, #16]
  53:srcc/gpio.c   **** 		//PxSEL0ºÍPxSEL1Î»Îª00Ê±±íÊ¾¸´ÓÃGPIO¹¦ÄÜ
  54:srcc/gpio.c   **** 		BCLR(pin,gpio_not_ptr->SEL0);
 233              		.loc 2 54 0
 234 00c6 3B69     		ldr	r3, [r7, #16]
 235 00c8 5B89     		ldrh	r3, [r3, #10]	@ movhi
 236 00ca 9BB2     		uxth	r3, r3
 237 00cc 1AB2     		sxth	r2, r3
 238 00ce BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 239 00d0 1946     		mov	r1, r3
 240 00d2 0123     		movs	r3, #1
 241 00d4 8B40     		lsls	r3, r3, r1
 242 00d6 1BB2     		sxth	r3, r3
 243 00d8 DB43     		mvns	r3, r3
 244 00da 1BB2     		sxth	r3, r3
 245 00dc 1340     		ands	r3, r3, r2
 246 00de 1BB2     		sxth	r3, r3
 247 00e0 9AB2     		uxth	r2, r3
 248 00e2 3B69     		ldr	r3, [r7, #16]
 249 00e4 5A81     		strh	r2, [r3, #10]	@ movhi
  55:srcc/gpio.c   **** 		BCLR(pin,gpio_not_ptr->SEL1);
 250              		.loc 2 55 0
 251 00e6 3B69     		ldr	r3, [r7, #16]
 252 00e8 9B89     		ldrh	r3, [r3, #12]	@ movhi
 253 00ea 9BB2     		uxth	r3, r3
 254 00ec 1AB2     		sxth	r2, r3
 255 00ee BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 256 00f0 1946     		mov	r1, r3
 257 00f2 0123     		movs	r3, #1
 258 00f4 8B40     		lsls	r3, r3, r1
 259 00f6 1BB2     		sxth	r3, r3
 260 00f8 DB43     		mvns	r3, r3
 261 00fa 1BB2     		sxth	r3, r3
 262 00fc 1340     		ands	r3, r3, r2
 263 00fe 1BB2     		sxth	r3, r3
 264 0100 9AB2     		uxth	r2, r3
 265 0102 3B69     		ldr	r3, [r7, #16]
 266 0104 9A81     		strh	r2, [r3, #12]	@ movhi
  56:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýdir£¬¾ö¶¨Òý½ÅÎªÊä³ö»¹ÊÇÊäÈë
  57:srcc/gpio.c   **** 	    if (1 == dir)   //Ï£ÍûÎªÊä³ö
 267              		.loc 2 57 0
 268 0106 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 269 0108 012B     		cmp	r3, #1
 270 010a 30D1     		bne	.L10
  58:srcc/gpio.c   **** 		{
  59:srcc/gpio.c   **** 			 BSET(pin,gpio_not_ptr->DIR);
 271              		.loc 2 59 0
 272 010c 3B69     		ldr	r3, [r7, #16]
 273 010e 9B88     		ldrh	r3, [r3, #4]	@ movhi
 274 0110 9BB2     		uxth	r3, r3
 275 0112 1AB2     		sxth	r2, r3
 276 0114 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 277 0116 1946     		mov	r1, r3
 278 0118 0123     		movs	r3, #1
 279 011a 8B40     		lsls	r3, r3, r1
 280 011c 1BB2     		sxth	r3, r3
 281 011e 1343     		orrs	r3, r3, r2
 282 0120 1BB2     		sxth	r3, r3
 283 0122 9AB2     		uxth	r2, r3
 284 0124 3B69     		ldr	r3, [r7, #16]
 285 0126 9A80     		strh	r2, [r3, #4]	@ movhi
  60:srcc/gpio.c   **** 			 if(1==state)//ÉèÖÃÊä³öµçÆ½¸ßµÍ
 286              		.loc 2 60 0
 287 0128 3B79     		ldrb	r3, [r7, #4]	@ zero_extendqisi2
 288 012a 012B     		cmp	r3, #1
 289 012c 0ED1     		bne	.L11
  61:srcc/gpio.c   **** 				 BSET(pin,gpio_even_ptr->OUT);
 290              		.loc 2 61 0
 291 012e FB68     		ldr	r3, [r7, #12]
 292 0130 DB78     		ldrb	r3, [r3, #3]
 293 0132 DBB2     		uxtb	r3, r3
 294 0134 5AB2     		sxtb	r2, r3
 295 0136 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 296 0138 1946     		mov	r1, r3
 297 013a 0123     		movs	r3, #1
 298 013c 8B40     		lsls	r3, r3, r1
 299 013e 5BB2     		sxtb	r3, r3
 300 0140 1343     		orrs	r3, r3, r2
 301 0142 5AB2     		sxtb	r2, r3
 302 0144 FB68     		ldr	r3, [r7, #12]
 303 0146 D2B2     		uxtb	r2, r2
 304 0148 DA70     		strb	r2, [r3, #3]
  62:srcc/gpio.c   **** 			 else
  63:srcc/gpio.c   **** 				 BCLR(pin,gpio_even_ptr->OUT);
  64:srcc/gpio.c   **** 		}
  65:srcc/gpio.c   **** 	    else           //Ï£ÍûÎªÊäÈë
  66:srcc/gpio.c   **** 		{
  67:srcc/gpio.c   **** 			 BCLR(pin,gpio_not_ptr->DIR);
  68:srcc/gpio.c   **** 		}
  69:srcc/gpio.c   **** 	}
  70:srcc/gpio.c   **** 	//ÊÇ·ñÊÇÅ¼Êý¶Ë¿Ú
  71:srcc/gpio.c   **** 	else if(port%2 == 0) //ÅÐ¶Ï¶Ë¿ÚºÅÊÇÆæÊý£¨gpio.hÖÐ¶Ô1~10µÄ±àºÅ´Ó0¿ªÊ¼£©
  72:srcc/gpio.c   **** 	{
  73:srcc/gpio.c   **** 		gpio_odd_ptr = (DIO_PORT_Odd_Interruptable_Type*) GPIO_ODD_ARR[port/2];
  74:srcc/gpio.c   **** 		//PxSEL0ºÍPxSEL1Î»Îª00Ê±±íÊ¾¸´ÓÃGPIO¹¦ÄÜ
  75:srcc/gpio.c   **** 		BCLR(pin,gpio_odd_ptr->SEL0);
  76:srcc/gpio.c   **** 		BCLR(pin,gpio_odd_ptr->SEL1);
  77:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýdir£¬¾ö¶¨Òý½ÅÎªÊä³ö»¹ÊÇÊäÈë
  78:srcc/gpio.c   **** 	    if (1 == dir)   //Ï£ÍûÎªÊä³ö
  79:srcc/gpio.c   **** 	    {
  80:srcc/gpio.c   **** 	    	BSET(pin,gpio_odd_ptr->DIR);  //ÉèÖÃÊä³ö·½Ïò¼Ä´æÆ÷ÎªÊä³ö
  81:srcc/gpio.c   **** 			if(1==state)//ÉèÖÃÊä³öµçÆ½¸ßµÍ
  82:srcc/gpio.c   **** 				BSET(pin,gpio_even_ptr->OUT);
  83:srcc/gpio.c   **** 			else
  84:srcc/gpio.c   **** 				BCLR(pin,gpio_even_ptr->OUT);
  85:srcc/gpio.c   **** 	    }
  86:srcc/gpio.c   **** 	    else           //Ï£ÍûÎªÊäÈë
  87:srcc/gpio.c   **** 	    {
  88:srcc/gpio.c   **** 	    	BCLR(pin,gpio_odd_ptr->DIR);
  89:srcc/gpio.c   **** 	    }
  90:srcc/gpio.c   **** 	}
  91:srcc/gpio.c   **** 	//ÊÇ·ñÊÇÆæÊý¶Ë¿Ú
  92:srcc/gpio.c   **** 	else
  93:srcc/gpio.c   **** 	{
  94:srcc/gpio.c   **** 		gpio_even_ptr = (DIO_PORT_Even_Interruptable_Type*)(GPIO_EVEN_ARR[(port-1)/2]);
  95:srcc/gpio.c   **** 		//PxSEL0ºÍPxSEL1Î»Îª00Ê±±íÊ¾¸´ÓÃGPIO¹¦ÄÜ
  96:srcc/gpio.c   **** 		BCLR(pin,gpio_even_ptr->SEL0);
  97:srcc/gpio.c   **** 		BCLR(pin,gpio_even_ptr->SEL1);
  98:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýdir£¬¾ö¶¨Òý½ÅÎªÊä³ö»¹ÊÇÊäÈë
  99:srcc/gpio.c   **** 	    if (1 == dir)           //Ï£ÍûÎªÊä³ö
 100:srcc/gpio.c   **** 	    {
 101:srcc/gpio.c   **** 	    	BSET(pin,gpio_even_ptr->DIR);   //ÉèÖÃÊä³ö·½Ïò¼Ä´æÆ÷ÎªÊä³ö
 102:srcc/gpio.c   **** 			if(1==state)//ÉèÖÃÊä³öµçÆ½¸ßµÍ
 103:srcc/gpio.c   **** 				BSET(pin,gpio_even_ptr->OUT);
 104:srcc/gpio.c   **** 			else
 105:srcc/gpio.c   **** 				BCLR(pin,gpio_even_ptr->OUT);
 106:srcc/gpio.c   **** 	    }
 107:srcc/gpio.c   **** 	    else                    //Ï£ÍûÎªÊäÈë
 108:srcc/gpio.c   **** 	    {
 109:srcc/gpio.c   **** 	    	BCLR(pin,gpio_even_ptr->DIR);
 110:srcc/gpio.c   **** 	    }
 111:srcc/gpio.c   **** 	}
 112:srcc/gpio.c   **** }
 305              		.loc 2 112 0
 306 014a 09E1     		b	.L23
 307              	.L11:
  63:srcc/gpio.c   **** 		}
 308              		.loc 2 63 0
 309 014c FB68     		ldr	r3, [r7, #12]
 310 014e DB78     		ldrb	r3, [r3, #3]
 311 0150 DBB2     		uxtb	r3, r3
 312 0152 5AB2     		sxtb	r2, r3
 313 0154 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 314 0156 1946     		mov	r1, r3
 315 0158 0123     		movs	r3, #1
 316 015a 8B40     		lsls	r3, r3, r1
 317 015c 5BB2     		sxtb	r3, r3
 318 015e DB43     		mvns	r3, r3
 319 0160 5BB2     		sxtb	r3, r3
 320 0162 1340     		ands	r3, r3, r2
 321 0164 5AB2     		sxtb	r2, r3
 322 0166 FB68     		ldr	r3, [r7, #12]
 323 0168 D2B2     		uxtb	r2, r2
 324 016a DA70     		strb	r2, [r3, #3]
 325              		.loc 2 112 0
 326 016c F8E0     		b	.L23
 327              	.L10:
  67:srcc/gpio.c   **** 		}
 328              		.loc 2 67 0
 329 016e 3B69     		ldr	r3, [r7, #16]
 330 0170 9B88     		ldrh	r3, [r3, #4]	@ movhi
 331 0172 9BB2     		uxth	r3, r3
 332 0174 1AB2     		sxth	r2, r3
 333 0176 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 334 0178 1946     		mov	r1, r3
 335 017a 0123     		movs	r3, #1
 336 017c 8B40     		lsls	r3, r3, r1
 337 017e 1BB2     		sxth	r3, r3
 338 0180 DB43     		mvns	r3, r3
 339 0182 1BB2     		sxth	r3, r3
 340 0184 1340     		ands	r3, r3, r2
 341 0186 1BB2     		sxth	r3, r3
 342 0188 9AB2     		uxth	r2, r3
 343 018a 3B69     		ldr	r3, [r7, #16]
 344 018c 9A80     		strh	r2, [r3, #4]	@ movhi
 345              		.loc 2 112 0
 346 018e E7E0     		b	.L23
 347              	.L9:
  71:srcc/gpio.c   **** 	{
 348              		.loc 2 71 0
 349 0190 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 350 0192 03F00103 		and	r3, r3, #1
 351 0196 DBB2     		uxtb	r3, r3
 352 0198 002B     		cmp	r3, #0
 353 019a 6CD1     		bne	.L15
  73:srcc/gpio.c   **** 		//PxSEL0ºÍPxSEL1Î»Îª00Ê±±íÊ¾¸´ÓÃGPIO¹¦ÄÜ
 354              		.loc 2 73 0
 355 019c FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 356 019e 5B08     		lsrs	r3, r3, #1
 357 01a0 DBB2     		uxtb	r3, r3
 358 01a2 1A46     		mov	r2, r3
 359 01a4 644B     		ldr	r3, .L24+4
 360 01a6 53F82230 		ldr	r3, [r3, r2, lsl #2]
 361 01aa 7B61     		str	r3, [r7, #20]
  75:srcc/gpio.c   **** 		BCLR(pin,gpio_odd_ptr->SEL1);
 362              		.loc 2 75 0
 363 01ac 7B69     		ldr	r3, [r7, #20]
 364 01ae 9B7A     		ldrb	r3, [r3, #10]
 365 01b0 DBB2     		uxtb	r3, r3
 366 01b2 5AB2     		sxtb	r2, r3
 367 01b4 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 368 01b6 1946     		mov	r1, r3
 369 01b8 0123     		movs	r3, #1
 370 01ba 8B40     		lsls	r3, r3, r1
 371 01bc 5BB2     		sxtb	r3, r3
 372 01be DB43     		mvns	r3, r3
 373 01c0 5BB2     		sxtb	r3, r3
 374 01c2 1340     		ands	r3, r3, r2
 375 01c4 5BB2     		sxtb	r3, r3
 376 01c6 DAB2     		uxtb	r2, r3
 377 01c8 7B69     		ldr	r3, [r7, #20]
 378 01ca 9A72     		strb	r2, [r3, #10]
  76:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýdir£¬¾ö¶¨Òý½ÅÎªÊä³ö»¹ÊÇÊäÈë
 379              		.loc 2 76 0
 380 01cc 7B69     		ldr	r3, [r7, #20]
 381 01ce 1B7B     		ldrb	r3, [r3, #12]
 382 01d0 DBB2     		uxtb	r3, r3
 383 01d2 5AB2     		sxtb	r2, r3
 384 01d4 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 385 01d6 1946     		mov	r1, r3
 386 01d8 0123     		movs	r3, #1
 387 01da 8B40     		lsls	r3, r3, r1
 388 01dc 5BB2     		sxtb	r3, r3
 389 01de DB43     		mvns	r3, r3
 390 01e0 5BB2     		sxtb	r3, r3
 391 01e2 1340     		ands	r3, r3, r2
 392 01e4 5BB2     		sxtb	r3, r3
 393 01e6 DAB2     		uxtb	r2, r3
 394 01e8 7B69     		ldr	r3, [r7, #20]
 395 01ea 1A73     		strb	r2, [r3, #12]
  78:srcc/gpio.c   **** 	    {
 396              		.loc 2 78 0
 397 01ec 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 398 01ee 012B     		cmp	r3, #1
 399 01f0 30D1     		bne	.L16
  80:srcc/gpio.c   **** 			if(1==state)//ÉèÖÃÊä³öµçÆ½¸ßµÍ
 400              		.loc 2 80 0
 401 01f2 7B69     		ldr	r3, [r7, #20]
 402 01f4 1B79     		ldrb	r3, [r3, #4]
 403 01f6 DBB2     		uxtb	r3, r3
 404 01f8 5AB2     		sxtb	r2, r3
 405 01fa BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 406 01fc 1946     		mov	r1, r3
 407 01fe 0123     		movs	r3, #1
 408 0200 8B40     		lsls	r3, r3, r1
 409 0202 5BB2     		sxtb	r3, r3
 410 0204 1343     		orrs	r3, r3, r2
 411 0206 5BB2     		sxtb	r3, r3
 412 0208 DAB2     		uxtb	r2, r3
 413 020a 7B69     		ldr	r3, [r7, #20]
 414 020c 1A71     		strb	r2, [r3, #4]
  81:srcc/gpio.c   **** 				BSET(pin,gpio_even_ptr->OUT);
 415              		.loc 2 81 0
 416 020e 3B79     		ldrb	r3, [r7, #4]	@ zero_extendqisi2
 417 0210 012B     		cmp	r3, #1
 418 0212 0ED1     		bne	.L17
  82:srcc/gpio.c   **** 			else
 419              		.loc 2 82 0
 420 0214 FB68     		ldr	r3, [r7, #12]
 421 0216 DB78     		ldrb	r3, [r3, #3]
 422 0218 DBB2     		uxtb	r3, r3
 423 021a 5AB2     		sxtb	r2, r3
 424 021c BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 425 021e 1946     		mov	r1, r3
 426 0220 0123     		movs	r3, #1
 427 0222 8B40     		lsls	r3, r3, r1
 428 0224 5BB2     		sxtb	r3, r3
 429 0226 1343     		orrs	r3, r3, r2
 430 0228 5AB2     		sxtb	r2, r3
 431 022a FB68     		ldr	r3, [r7, #12]
 432 022c D2B2     		uxtb	r2, r2
 433 022e DA70     		strb	r2, [r3, #3]
 434              		.loc 2 112 0
 435 0230 96E0     		b	.L23
 436              	.L17:
  84:srcc/gpio.c   **** 	    }
 437              		.loc 2 84 0
 438 0232 FB68     		ldr	r3, [r7, #12]
 439 0234 DB78     		ldrb	r3, [r3, #3]
 440 0236 DBB2     		uxtb	r3, r3
 441 0238 5AB2     		sxtb	r2, r3
 442 023a BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 443 023c 1946     		mov	r1, r3
 444 023e 0123     		movs	r3, #1
 445 0240 8B40     		lsls	r3, r3, r1
 446 0242 5BB2     		sxtb	r3, r3
 447 0244 DB43     		mvns	r3, r3
 448 0246 5BB2     		sxtb	r3, r3
 449 0248 1340     		ands	r3, r3, r2
 450 024a 5AB2     		sxtb	r2, r3
 451 024c FB68     		ldr	r3, [r7, #12]
 452 024e D2B2     		uxtb	r2, r2
 453 0250 DA70     		strb	r2, [r3, #3]
 454              		.loc 2 112 0
 455 0252 85E0     		b	.L23
 456              	.L16:
  88:srcc/gpio.c   **** 	    }
 457              		.loc 2 88 0
 458 0254 7B69     		ldr	r3, [r7, #20]
 459 0256 1B79     		ldrb	r3, [r3, #4]
 460 0258 DBB2     		uxtb	r3, r3
 461 025a 5AB2     		sxtb	r2, r3
 462 025c BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 463 025e 1946     		mov	r1, r3
 464 0260 0123     		movs	r3, #1
 465 0262 8B40     		lsls	r3, r3, r1
 466 0264 5BB2     		sxtb	r3, r3
 467 0266 DB43     		mvns	r3, r3
 468 0268 5BB2     		sxtb	r3, r3
 469 026a 1340     		ands	r3, r3, r2
 470 026c 5BB2     		sxtb	r3, r3
 471 026e DAB2     		uxtb	r2, r3
 472 0270 7B69     		ldr	r3, [r7, #20]
 473 0272 1A71     		strb	r2, [r3, #4]
 474              		.loc 2 112 0
 475 0274 74E0     		b	.L23
 476              	.L15:
  94:srcc/gpio.c   **** 		//PxSEL0ºÍPxSEL1Î»Îª00Ê±±íÊ¾¸´ÓÃGPIO¹¦ÄÜ
 477              		.loc 2 94 0
 478 0276 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 479 0278 013B     		subs	r3, r3, #1
 480 027a DA0F     		lsrs	r2, r3, #31
 481 027c 1344     		add	r3, r3, r2
 482 027e 5B10     		asrs	r3, r3, #1
 483 0280 1A46     		mov	r2, r3
 484 0282 2E4B     		ldr	r3, .L24+8
 485 0284 53F82230 		ldr	r3, [r3, r2, lsl #2]
 486 0288 FB60     		str	r3, [r7, #12]
  96:srcc/gpio.c   **** 		BCLR(pin,gpio_even_ptr->SEL1);
 487              		.loc 2 96 0
 488 028a FB68     		ldr	r3, [r7, #12]
 489 028c DB7A     		ldrb	r3, [r3, #11]
 490 028e DBB2     		uxtb	r3, r3
 491 0290 5AB2     		sxtb	r2, r3
 492 0292 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 493 0294 1946     		mov	r1, r3
 494 0296 0123     		movs	r3, #1
 495 0298 8B40     		lsls	r3, r3, r1
 496 029a 5BB2     		sxtb	r3, r3
 497 029c DB43     		mvns	r3, r3
 498 029e 5BB2     		sxtb	r3, r3
 499 02a0 1340     		ands	r3, r3, r2
 500 02a2 5AB2     		sxtb	r2, r3
 501 02a4 FB68     		ldr	r3, [r7, #12]
 502 02a6 D2B2     		uxtb	r2, r2
 503 02a8 DA72     		strb	r2, [r3, #11]
  97:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýdir£¬¾ö¶¨Òý½ÅÎªÊä³ö»¹ÊÇÊäÈë
 504              		.loc 2 97 0
 505 02aa FB68     		ldr	r3, [r7, #12]
 506 02ac 5B7B     		ldrb	r3, [r3, #13]
 507 02ae DBB2     		uxtb	r3, r3
 508 02b0 5AB2     		sxtb	r2, r3
 509 02b2 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 510 02b4 1946     		mov	r1, r3
 511 02b6 0123     		movs	r3, #1
 512 02b8 8B40     		lsls	r3, r3, r1
 513 02ba 5BB2     		sxtb	r3, r3
 514 02bc DB43     		mvns	r3, r3
 515 02be 5BB2     		sxtb	r3, r3
 516 02c0 1340     		ands	r3, r3, r2
 517 02c2 5AB2     		sxtb	r2, r3
 518 02c4 FB68     		ldr	r3, [r7, #12]
 519 02c6 D2B2     		uxtb	r2, r2
 520 02c8 5A73     		strb	r2, [r3, #13]
  99:srcc/gpio.c   **** 	    {
 521              		.loc 2 99 0
 522 02ca 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 523 02cc 012B     		cmp	r3, #1
 524 02ce 37D1     		bne	.L20
 101:srcc/gpio.c   **** 			if(1==state)//ÉèÖÃÊä³öµçÆ½¸ßµÍ
 525              		.loc 2 101 0
 526 02d0 FB68     		ldr	r3, [r7, #12]
 527 02d2 5B79     		ldrb	r3, [r3, #5]
 528 02d4 DBB2     		uxtb	r3, r3
 529 02d6 5AB2     		sxtb	r2, r3
 530 02d8 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 531 02da 1946     		mov	r1, r3
 532 02dc 0123     		movs	r3, #1
 533 02de 8B40     		lsls	r3, r3, r1
 534 02e0 5BB2     		sxtb	r3, r3
 535 02e2 1343     		orrs	r3, r3, r2
 536 02e4 5AB2     		sxtb	r2, r3
 537 02e6 FB68     		ldr	r3, [r7, #12]
 538 02e8 D2B2     		uxtb	r2, r2
 539 02ea 5A71     		strb	r2, [r3, #5]
 102:srcc/gpio.c   **** 				BSET(pin,gpio_even_ptr->OUT);
 540              		.loc 2 102 0
 541 02ec 3B79     		ldrb	r3, [r7, #4]	@ zero_extendqisi2
 542 02ee 012B     		cmp	r3, #1
 543 02f0 0ED1     		bne	.L21
 103:srcc/gpio.c   **** 			else
 544              		.loc 2 103 0
 545 02f2 FB68     		ldr	r3, [r7, #12]
 546 02f4 DB78     		ldrb	r3, [r3, #3]
 547 02f6 DBB2     		uxtb	r3, r3
 548 02f8 5AB2     		sxtb	r2, r3
 549 02fa BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 550 02fc 1946     		mov	r1, r3
 551 02fe 0123     		movs	r3, #1
 552 0300 8B40     		lsls	r3, r3, r1
 553 0302 5BB2     		sxtb	r3, r3
 554 0304 1343     		orrs	r3, r3, r2
 555 0306 5AB2     		sxtb	r2, r3
 556 0308 FB68     		ldr	r3, [r7, #12]
 557 030a D2B2     		uxtb	r2, r2
 558 030c DA70     		strb	r2, [r3, #3]
 559              		.loc 2 112 0
 560 030e 27E0     		b	.L23
 561              	.L21:
 105:srcc/gpio.c   **** 	    }
 562              		.loc 2 105 0
 563 0310 FB68     		ldr	r3, [r7, #12]
 564 0312 DB78     		ldrb	r3, [r3, #3]
 565 0314 DBB2     		uxtb	r3, r3
 566 0316 5AB2     		sxtb	r2, r3
 567 0318 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 568 031a 1946     		mov	r1, r3
 569 031c 0123     		movs	r3, #1
 570 031e 8B40     		lsls	r3, r3, r1
 571 0320 5BB2     		sxtb	r3, r3
 572 0322 DB43     		mvns	r3, r3
 573 0324 5BB2     		sxtb	r3, r3
 574 0326 1340     		ands	r3, r3, r2
 575 0328 5AB2     		sxtb	r2, r3
 576 032a FB68     		ldr	r3, [r7, #12]
 577 032c D2B2     		uxtb	r2, r2
 578 032e DA70     		strb	r2, [r3, #3]
 579              		.loc 2 112 0
 580 0330 16E0     		b	.L23
 581              	.L25:
 582 0332 00BF     		.align	2
 583              	.L24:
 584 0334 204D0040 		.word	1073761568
 585 0338 00000000 		.word	GPIO_ODD_ARR
 586 033c 00000000 		.word	GPIO_EVEN_ARR
 587              	.L20:
 109:srcc/gpio.c   **** 	    }
 588              		.loc 2 109 0
 589 0340 FB68     		ldr	r3, [r7, #12]
 590 0342 5B79     		ldrb	r3, [r3, #5]
 591 0344 DBB2     		uxtb	r3, r3
 592 0346 5AB2     		sxtb	r2, r3
 593 0348 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 594 034a 1946     		mov	r1, r3
 595 034c 0123     		movs	r3, #1
 596 034e 8B40     		lsls	r3, r3, r1
 597 0350 5BB2     		sxtb	r3, r3
 598 0352 DB43     		mvns	r3, r3
 599 0354 5BB2     		sxtb	r3, r3
 600 0356 1340     		ands	r3, r3, r2
 601 0358 5AB2     		sxtb	r2, r3
 602 035a FB68     		ldr	r3, [r7, #12]
 603 035c D2B2     		uxtb	r2, r2
 604 035e 5A71     		strb	r2, [r3, #5]
 605              	.L23:
 606              		.loc 2 112 0
 607 0360 00BF     		nop
 608 0362 1837     		adds	r7, r7, #24
 609              		.cfi_def_cfa_offset 8
 610 0364 BD46     		mov	sp, r7
 611              		.cfi_def_cfa_register 13
 612              		@ sp needed
 613 0366 80BD     		pop	{r7, pc}
 614              		.cfi_endproc
 615              	.LFE124:
 617              		.align	1
 618              		.global	gpio_set
 619              		.syntax unified
 620              		.thumb
 621              		.thumb_func
 622              		.fpu fpv4-sp-d16
 624              	gpio_set:
 625              	.LFB125:
 113:srcc/gpio.c   **** 
 114:srcc/gpio.c   **** //===========================================================================
 115:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_set
 116:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
 117:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º¶Ë¿ÚºÅ|Òý½ÅºÅ(PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
 118:srcc/gpio.c   **** //         state£ºÒý½Å³õÊ¼×´Ì¬£¨0=µÍµçÆ½£¬1=¸ßµçÆ½£©
 119:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£ºÉè¶¨Òý½Å×´Ì¬ÎªµÍµçÆ½»ò¸ßµçÆ½
 120:srcc/gpio.c   **** //===========================================================================
 121:srcc/gpio.c   **** void gpio_set(uint16_t port_pin, uint8_t state)
 122:srcc/gpio.c   **** {
 626              		.loc 2 122 0
 627              		.cfi_startproc
 628              		@ args = 0, pretend = 0, frame = 24
 629              		@ frame_needed = 1, uses_anonymous_args = 0
 630 0368 80B5     		push	{r7, lr}
 631              		.cfi_def_cfa_offset 8
 632              		.cfi_offset 7, -8
 633              		.cfi_offset 14, -4
 634 036a 86B0     		sub	sp, sp, #24
 635              		.cfi_def_cfa_offset 32
 636 036c 00AF     		add	r7, sp, #0
 637              		.cfi_def_cfa_register 7
 638 036e 0346     		mov	r3, r0
 639 0370 0A46     		mov	r2, r1
 640 0372 FB80     		strh	r3, [r7, #6]	@ movhi
 641 0374 1346     		mov	r3, r2
 642 0376 7B71     		strb	r3, [r7, #5]
 123:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
 124:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
 125:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
 126:srcc/gpio.c   **** 	DIO_PORT_Not_Interruptable_Type* gpio_not_ptr;
 127:srcc/gpio.c   **** 	uint8_t port;
 128:srcc/gpio.c   **** 	uint8_t pin;
 129:srcc/gpio.c   **** 
 130:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 643              		.loc 2 130 0
 644 0378 07F10A02 		add	r2, r7, #10
 645 037c 07F10B01 		add	r1, r7, #11
 646 0380 FB88     		ldrh	r3, [r7, #6]
 647 0382 1846     		mov	r0, r3
 648 0384 FFF770FE 		bl	gpio_port_pin_resolution
 131:srcc/gpio.c   **** 	//ÅÐ¶ÏÊÇ·ñÎªJ¿Ú
 132:srcc/gpio.c   **** 	if(port >= 10)
 649              		.loc 2 132 0
 650 0388 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 651 038a 092B     		cmp	r3, #9
 652 038c 24D9     		bls	.L27
 133:srcc/gpio.c   **** 	{
 134:srcc/gpio.c   **** 		gpio_not_ptr =PJ;
 653              		.loc 2 134 0
 654 038e 434B     		ldr	r3, .L36
 655 0390 FB60     		str	r3, [r7, #12]
 135:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýstate£¬¾ö¶¨Òý½ÅÎªÊä³ö1»¹ÊÇ0
 136:srcc/gpio.c   **** 		if (1==state)
 656              		.loc 2 136 0
 657 0392 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 658 0394 012B     		cmp	r3, #1
 659 0396 0ED1     		bne	.L28
 137:srcc/gpio.c   **** 		{
 138:srcc/gpio.c   **** 			BSET(pin,gpio_not_ptr->OUT);
 660              		.loc 2 138 0
 661 0398 FB68     		ldr	r3, [r7, #12]
 662 039a 5B88     		ldrh	r3, [r3, #2]	@ movhi
 663 039c 9BB2     		uxth	r3, r3
 664 039e 1AB2     		sxth	r2, r3
 665 03a0 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 666 03a2 1946     		mov	r1, r3
 667 03a4 0123     		movs	r3, #1
 668 03a6 8B40     		lsls	r3, r3, r1
 669 03a8 1BB2     		sxth	r3, r3
 670 03aa 1343     		orrs	r3, r3, r2
 671 03ac 1BB2     		sxth	r3, r3
 672 03ae 9AB2     		uxth	r2, r3
 673 03b0 FB68     		ldr	r3, [r7, #12]
 674 03b2 5A80     		strh	r2, [r3, #2]	@ movhi
 139:srcc/gpio.c   **** 		}
 140:srcc/gpio.c   **** 			else
 141:srcc/gpio.c   **** 		{
 142:srcc/gpio.c   **** 			BCLR(pin,gpio_not_ptr->OUT);
 143:srcc/gpio.c   **** 		}
 144:srcc/gpio.c   **** 	}
 145:srcc/gpio.c   **** 	else if(port%2 == 0)
 146:srcc/gpio.c   **** 	{
 147:srcc/gpio.c   **** 		gpio_odd_ptr = (DIO_PORT_Odd_Interruptable_Type*) GPIO_ODD_ARR[port/2];
 148:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýstate£¬¾ö¶¨Òý½ÅÎªÊä³ö1»¹ÊÇ0
 149:srcc/gpio.c   **** 		if (1==state)
 150:srcc/gpio.c   **** 		{
 151:srcc/gpio.c   **** 			BSET(pin,gpio_odd_ptr->OUT);
 152:srcc/gpio.c   **** 		}
 153:srcc/gpio.c   **** 		else
 154:srcc/gpio.c   **** 		{
 155:srcc/gpio.c   **** 			BCLR(pin,gpio_odd_ptr->OUT);
 156:srcc/gpio.c   **** 		}
 157:srcc/gpio.c   **** 	}
 158:srcc/gpio.c   **** 	else
 159:srcc/gpio.c   **** 	{
 160:srcc/gpio.c   **** 		gpio_even_ptr =(DIO_PORT_Even_Interruptable_Type*) (GPIO_EVEN_ARR[(port-1)/2]);
 161:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýstate£¬¾ö¶¨Òý½ÅÎªÊä³ö1»¹ÊÇ0
 162:srcc/gpio.c   **** 		if (1==state)
 163:srcc/gpio.c   **** 		{
 164:srcc/gpio.c   **** 			BSET(pin,gpio_even_ptr->OUT);
 165:srcc/gpio.c   **** 		}
 166:srcc/gpio.c   **** 		else
 167:srcc/gpio.c   **** 		{
 168:srcc/gpio.c   **** 			BCLR(pin,gpio_even_ptr->OUT);
 169:srcc/gpio.c   **** 		}
 170:srcc/gpio.c   **** 	}
 171:srcc/gpio.c   **** 
 172:srcc/gpio.c   **** }
 675              		.loc 2 172 0
 676 03b4 6DE0     		b	.L35
 677              	.L28:
 142:srcc/gpio.c   **** 		}
 678              		.loc 2 142 0
 679 03b6 FB68     		ldr	r3, [r7, #12]
 680 03b8 5B88     		ldrh	r3, [r3, #2]	@ movhi
 681 03ba 9BB2     		uxth	r3, r3
 682 03bc 1AB2     		sxth	r2, r3
 683 03be BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 684 03c0 1946     		mov	r1, r3
 685 03c2 0123     		movs	r3, #1
 686 03c4 8B40     		lsls	r3, r3, r1
 687 03c6 1BB2     		sxth	r3, r3
 688 03c8 DB43     		mvns	r3, r3
 689 03ca 1BB2     		sxth	r3, r3
 690 03cc 1340     		ands	r3, r3, r2
 691 03ce 1BB2     		sxth	r3, r3
 692 03d0 9AB2     		uxth	r2, r3
 693 03d2 FB68     		ldr	r3, [r7, #12]
 694 03d4 5A80     		strh	r2, [r3, #2]	@ movhi
 695              		.loc 2 172 0
 696 03d6 5CE0     		b	.L35
 697              	.L27:
 145:srcc/gpio.c   **** 	{
 698              		.loc 2 145 0
 699 03d8 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 700 03da 03F00103 		and	r3, r3, #1
 701 03de DBB2     		uxtb	r3, r3
 702 03e0 002B     		cmp	r3, #0
 703 03e2 2AD1     		bne	.L31
 147:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýstate£¬¾ö¶¨Òý½ÅÎªÊä³ö1»¹ÊÇ0
 704              		.loc 2 147 0
 705 03e4 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 706 03e6 5B08     		lsrs	r3, r3, #1
 707 03e8 DBB2     		uxtb	r3, r3
 708 03ea 1A46     		mov	r2, r3
 709 03ec 2C4B     		ldr	r3, .L36+4
 710 03ee 53F82230 		ldr	r3, [r3, r2, lsl #2]
 711 03f2 3B61     		str	r3, [r7, #16]
 149:srcc/gpio.c   **** 		{
 712              		.loc 2 149 0
 713 03f4 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 714 03f6 012B     		cmp	r3, #1
 715 03f8 0ED1     		bne	.L32
 151:srcc/gpio.c   **** 		}
 716              		.loc 2 151 0
 717 03fa 3B69     		ldr	r3, [r7, #16]
 718 03fc 9B78     		ldrb	r3, [r3, #2]
 719 03fe DBB2     		uxtb	r3, r3
 720 0400 5AB2     		sxtb	r2, r3
 721 0402 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 722 0404 1946     		mov	r1, r3
 723 0406 0123     		movs	r3, #1
 724 0408 8B40     		lsls	r3, r3, r1
 725 040a 5BB2     		sxtb	r3, r3
 726 040c 1343     		orrs	r3, r3, r2
 727 040e 5BB2     		sxtb	r3, r3
 728 0410 DAB2     		uxtb	r2, r3
 729 0412 3B69     		ldr	r3, [r7, #16]
 730 0414 9A70     		strb	r2, [r3, #2]
 731              		.loc 2 172 0
 732 0416 3CE0     		b	.L35
 733              	.L32:
 155:srcc/gpio.c   **** 		}
 734              		.loc 2 155 0
 735 0418 3B69     		ldr	r3, [r7, #16]
 736 041a 9B78     		ldrb	r3, [r3, #2]
 737 041c DBB2     		uxtb	r3, r3
 738 041e 5AB2     		sxtb	r2, r3
 739 0420 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 740 0422 1946     		mov	r1, r3
 741 0424 0123     		movs	r3, #1
 742 0426 8B40     		lsls	r3, r3, r1
 743 0428 5BB2     		sxtb	r3, r3
 744 042a DB43     		mvns	r3, r3
 745 042c 5BB2     		sxtb	r3, r3
 746 042e 1340     		ands	r3, r3, r2
 747 0430 5BB2     		sxtb	r3, r3
 748 0432 DAB2     		uxtb	r2, r3
 749 0434 3B69     		ldr	r3, [r7, #16]
 750 0436 9A70     		strb	r2, [r3, #2]
 751              		.loc 2 172 0
 752 0438 2BE0     		b	.L35
 753              	.L31:
 160:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýstate£¬¾ö¶¨Òý½ÅÎªÊä³ö1»¹ÊÇ0
 754              		.loc 2 160 0
 755 043a FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 756 043c 013B     		subs	r3, r3, #1
 757 043e DA0F     		lsrs	r2, r3, #31
 758 0440 1344     		add	r3, r3, r2
 759 0442 5B10     		asrs	r3, r3, #1
 760 0444 1A46     		mov	r2, r3
 761 0446 174B     		ldr	r3, .L36+8
 762 0448 53F82230 		ldr	r3, [r3, r2, lsl #2]
 763 044c 7B61     		str	r3, [r7, #20]
 162:srcc/gpio.c   **** 		{
 764              		.loc 2 162 0
 765 044e 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 766 0450 012B     		cmp	r3, #1
 767 0452 0ED1     		bne	.L34
 164:srcc/gpio.c   **** 		}
 768              		.loc 2 164 0
 769 0454 7B69     		ldr	r3, [r7, #20]
 770 0456 DB78     		ldrb	r3, [r3, #3]
 771 0458 DBB2     		uxtb	r3, r3
 772 045a 5AB2     		sxtb	r2, r3
 773 045c BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 774 045e 1946     		mov	r1, r3
 775 0460 0123     		movs	r3, #1
 776 0462 8B40     		lsls	r3, r3, r1
 777 0464 5BB2     		sxtb	r3, r3
 778 0466 1343     		orrs	r3, r3, r2
 779 0468 5BB2     		sxtb	r3, r3
 780 046a DAB2     		uxtb	r2, r3
 781 046c 7B69     		ldr	r3, [r7, #20]
 782 046e DA70     		strb	r2, [r3, #3]
 783              		.loc 2 172 0
 784 0470 0FE0     		b	.L35
 785              	.L34:
 168:srcc/gpio.c   **** 		}
 786              		.loc 2 168 0
 787 0472 7B69     		ldr	r3, [r7, #20]
 788 0474 DB78     		ldrb	r3, [r3, #3]
 789 0476 DBB2     		uxtb	r3, r3
 790 0478 5AB2     		sxtb	r2, r3
 791 047a BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 792 047c 1946     		mov	r1, r3
 793 047e 0123     		movs	r3, #1
 794 0480 8B40     		lsls	r3, r3, r1
 795 0482 5BB2     		sxtb	r3, r3
 796 0484 DB43     		mvns	r3, r3
 797 0486 5BB2     		sxtb	r3, r3
 798 0488 1340     		ands	r3, r3, r2
 799 048a 5BB2     		sxtb	r3, r3
 800 048c DAB2     		uxtb	r2, r3
 801 048e 7B69     		ldr	r3, [r7, #20]
 802 0490 DA70     		strb	r2, [r3, #3]
 803              	.L35:
 804              		.loc 2 172 0
 805 0492 00BF     		nop
 806 0494 1837     		adds	r7, r7, #24
 807              		.cfi_def_cfa_offset 8
 808 0496 BD46     		mov	sp, r7
 809              		.cfi_def_cfa_register 13
 810              		@ sp needed
 811 0498 80BD     		pop	{r7, pc}
 812              	.L37:
 813 049a 00BF     		.align	2
 814              	.L36:
 815 049c 204D0040 		.word	1073761568
 816 04a0 00000000 		.word	GPIO_ODD_ARR
 817 04a4 00000000 		.word	GPIO_EVEN_ARR
 818              		.cfi_endproc
 819              	.LFE125:
 821              		.align	1
 822              		.global	gpio_get
 823              		.syntax unified
 824              		.thumb
 825              		.thumb_func
 826              		.fpu fpv4-sp-d16
 828              	gpio_get:
 829              	.LFB126:
 173:srcc/gpio.c   **** 
 174:srcc/gpio.c   **** //===========================================================================
 175:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_get
 176:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÖ¸¶¨Òý½ÅµÄ×´Ì¬£¨1»ò0£©
 177:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º¶Ë¿ÚºÅ|Òý½ÅºÅ(PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
 178:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£º»ñÈ¡Ö¸¶¨Òý½ÅµÄ×´Ì¬£¨1»ò0£©
 179:srcc/gpio.c   **** //===========================================================================
 180:srcc/gpio.c   **** uint8_t gpio_get(uint16_t port_pin)
 181:srcc/gpio.c   **** {
 830              		.loc 2 181 0
 831              		.cfi_startproc
 832              		@ args = 0, pretend = 0, frame = 24
 833              		@ frame_needed = 1, uses_anonymous_args = 0
 834 04a8 80B5     		push	{r7, lr}
 835              		.cfi_def_cfa_offset 8
 836              		.cfi_offset 7, -8
 837              		.cfi_offset 14, -4
 838 04aa 86B0     		sub	sp, sp, #24
 839              		.cfi_def_cfa_offset 32
 840 04ac 00AF     		add	r7, sp, #0
 841              		.cfi_def_cfa_register 7
 842 04ae 0346     		mov	r3, r0
 843 04b0 FB80     		strh	r3, [r7, #6]	@ movhi
 182:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
 183:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
 184:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
 185:srcc/gpio.c   **** 	DIO_PORT_Not_Interruptable_Type* gpio_not_ptr;
 186:srcc/gpio.c   **** 	uint8_t port;
 187:srcc/gpio.c   **** 	uint8_t pin;
 188:srcc/gpio.c   **** 	//½âÎö¶Ë¿ÚºÍÒý½Å
 189:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 844              		.loc 2 189 0
 845 04b2 07F10A02 		add	r2, r7, #10
 846 04b6 07F10B01 		add	r1, r7, #11
 847 04ba FB88     		ldrh	r3, [r7, #6]
 848 04bc 1846     		mov	r0, r3
 849 04be FFF7D3FD 		bl	gpio_port_pin_resolution
 190:srcc/gpio.c   **** 
 191:srcc/gpio.c   **** 	if(port >= 10)
 850              		.loc 2 191 0
 851 04c2 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 852 04c4 092B     		cmp	r3, #9
 853 04c6 10D9     		bls	.L39
 192:srcc/gpio.c   **** 	{
 193:srcc/gpio.c   **** 		gpio_not_ptr = (DIO_PORT_Not_Interruptable_Type*)PJ;
 854              		.loc 2 193 0
 855 04c8 244B     		ldr	r3, .L46
 856 04ca FB60     		str	r3, [r7, #12]
 194:srcc/gpio.c   **** 		//·µ»ØÒý½ÅµÄ×´Ì¬
 195:srcc/gpio.c   **** 		if(BGET(pin,gpio_not_ptr->DIR))
 857              		.loc 2 195 0
 858 04cc FB68     		ldr	r3, [r7, #12]
 859 04ce 9B88     		ldrh	r3, [r3, #4]	@ movhi
 860 04d0 9BB2     		uxth	r3, r3
 861 04d2 1A46     		mov	r2, r3
 862 04d4 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 863 04d6 42FA03F3 		asr	r3, r2, r3
 864 04da 03F00103 		and	r3, r3, #1
 865 04de 002B     		cmp	r3, #0
 866 04e0 01D0     		beq	.L40
 196:srcc/gpio.c   **** 		{
 197:srcc/gpio.c   **** 			return 1;
 867              		.loc 2 197 0
 868 04e2 0123     		movs	r3, #1
 869 04e4 36E0     		b	.L45
 870              	.L40:
 198:srcc/gpio.c   **** 		}
 199:srcc/gpio.c   **** 		else
 200:srcc/gpio.c   **** 		{
 201:srcc/gpio.c   **** 			return 0;
 871              		.loc 2 201 0
 872 04e6 0023     		movs	r3, #0
 873 04e8 34E0     		b	.L45
 874              	.L39:
 202:srcc/gpio.c   **** 		}
 203:srcc/gpio.c   **** 	}
 204:srcc/gpio.c   **** 	else if(port%2 == 0)
 875              		.loc 2 204 0
 876 04ea FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 877 04ec 03F00103 		and	r3, r3, #1
 878 04f0 DBB2     		uxtb	r3, r3
 879 04f2 002B     		cmp	r3, #0
 880 04f4 16D1     		bne	.L42
 205:srcc/gpio.c   **** 	{
 206:srcc/gpio.c   **** 		gpio_odd_ptr = (DIO_PORT_Odd_Interruptable_Type*) (GPIO_ODD_ARR[port/2]);
 881              		.loc 2 206 0
 882 04f6 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 883 04f8 5B08     		lsrs	r3, r3, #1
 884 04fa DBB2     		uxtb	r3, r3
 885 04fc 1A46     		mov	r2, r3
 886 04fe 184B     		ldr	r3, .L46+4
 887 0500 53F82230 		ldr	r3, [r3, r2, lsl #2]
 888 0504 3B61     		str	r3, [r7, #16]
 207:srcc/gpio.c   **** 		//·µ»ØÒý½ÅµÄ×´Ì¬
 208:srcc/gpio.c   **** 		if(BGET(pin,gpio_odd_ptr->DIR))
 889              		.loc 2 208 0
 890 0506 3B69     		ldr	r3, [r7, #16]
 891 0508 1B79     		ldrb	r3, [r3, #4]
 892 050a DBB2     		uxtb	r3, r3
 893 050c 1A46     		mov	r2, r3
 894 050e BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 895 0510 42FA03F3 		asr	r3, r2, r3
 896 0514 03F00103 		and	r3, r3, #1
 897 0518 002B     		cmp	r3, #0
 898 051a 01D0     		beq	.L43
 209:srcc/gpio.c   **** 		{
 210:srcc/gpio.c   **** 			return 1;
 899              		.loc 2 210 0
 900 051c 0123     		movs	r3, #1
 901 051e 19E0     		b	.L45
 902              	.L43:
 211:srcc/gpio.c   **** 		}
 212:srcc/gpio.c   **** 		else
 213:srcc/gpio.c   **** 		{
 214:srcc/gpio.c   **** 			return 0;
 903              		.loc 2 214 0
 904 0520 0023     		movs	r3, #0
 905 0522 17E0     		b	.L45
 906              	.L42:
 215:srcc/gpio.c   **** 		}
 216:srcc/gpio.c   **** 	}
 217:srcc/gpio.c   **** 	else
 218:srcc/gpio.c   **** 	{
 219:srcc/gpio.c   **** 		gpio_even_ptr = (DIO_PORT_Even_Interruptable_Type*) (GPIO_EVEN_ARR[(port-1)/2]);
 907              		.loc 2 219 0
 908 0524 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 909 0526 013B     		subs	r3, r3, #1
 910 0528 DA0F     		lsrs	r2, r3, #31
 911 052a 1344     		add	r3, r3, r2
 912 052c 5B10     		asrs	r3, r3, #1
 913 052e 1A46     		mov	r2, r3
 914 0530 0C4B     		ldr	r3, .L46+8
 915 0532 53F82230 		ldr	r3, [r3, r2, lsl #2]
 916 0536 7B61     		str	r3, [r7, #20]
 220:srcc/gpio.c   **** 		//·µ»ØÒý½ÅµÄ×´Ì¬
 221:srcc/gpio.c   **** 		if(BGET(pin,gpio_even_ptr->DIR))
 917              		.loc 2 221 0
 918 0538 7B69     		ldr	r3, [r7, #20]
 919 053a 5B79     		ldrb	r3, [r3, #5]
 920 053c DBB2     		uxtb	r3, r3
 921 053e 1A46     		mov	r2, r3
 922 0540 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 923 0542 42FA03F3 		asr	r3, r2, r3
 924 0546 03F00103 		and	r3, r3, #1
 925 054a 002B     		cmp	r3, #0
 926 054c 01D0     		beq	.L44
 222:srcc/gpio.c   **** 		{
 223:srcc/gpio.c   **** 			return 1;
 927              		.loc 2 223 0
 928 054e 0123     		movs	r3, #1
 929 0550 00E0     		b	.L45
 930              	.L44:
 224:srcc/gpio.c   **** 		}
 225:srcc/gpio.c   **** 		else
 226:srcc/gpio.c   **** 		{
 227:srcc/gpio.c   **** 			return 0;
 931              		.loc 2 227 0
 932 0552 0023     		movs	r3, #0
 933              	.L45:
 228:srcc/gpio.c   **** 		}
 229:srcc/gpio.c   **** 	}
 230:srcc/gpio.c   **** }
 934              		.loc 2 230 0
 935 0554 1846     		mov	r0, r3
 936 0556 1837     		adds	r7, r7, #24
 937              		.cfi_def_cfa_offset 8
 938 0558 BD46     		mov	sp, r7
 939              		.cfi_def_cfa_register 13
 940              		@ sp needed
 941 055a 80BD     		pop	{r7, pc}
 942              	.L47:
 943              		.align	2
 944              	.L46:
 945 055c 204D0040 		.word	1073761568
 946 0560 00000000 		.word	GPIO_ODD_ARR
 947 0564 00000000 		.word	GPIO_EVEN_ARR
 948              		.cfi_endproc
 949              	.LFE126:
 951              		.align	1
 952              		.global	gpio_reverse
 953              		.syntax unified
 954              		.thumb
 955              		.thumb_func
 956              		.fpu fpv4-sp-d16
 958              	gpio_reverse:
 959              	.LFB127:
 231:srcc/gpio.c   **** 
 232:srcc/gpio.c   **** //===========================================================================
 233:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_reverse
 234:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
 235:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º¶Ë¿ÚºÅ|Òý½ÅºÅ  (PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
 236:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£º·´×ªÖ¸¶¨Òý½ÅÊä³ö×´Ì¬¡£
 237:srcc/gpio.c   **** //===========================================================================
 238:srcc/gpio.c   **** void gpio_reverse(uint16_t port_pin)
 239:srcc/gpio.c   **** {
 960              		.loc 2 239 0
 961              		.cfi_startproc
 962              		@ args = 0, pretend = 0, frame = 24
 963              		@ frame_needed = 1, uses_anonymous_args = 0
 964 0568 80B5     		push	{r7, lr}
 965              		.cfi_def_cfa_offset 8
 966              		.cfi_offset 7, -8
 967              		.cfi_offset 14, -4
 968 056a 86B0     		sub	sp, sp, #24
 969              		.cfi_def_cfa_offset 32
 970 056c 00AF     		add	r7, sp, #0
 971              		.cfi_def_cfa_register 7
 972 056e 0346     		mov	r3, r0
 973 0570 FB80     		strh	r3, [r7, #6]	@ movhi
 240:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
 241:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
 242:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
 243:srcc/gpio.c   **** 	DIO_PORT_Not_Interruptable_Type* gpio_not_ptr;
 244:srcc/gpio.c   **** 	uint8_t port;
 245:srcc/gpio.c   **** 	uint8_t pin;
 246:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 974              		.loc 2 246 0
 975 0572 07F10A02 		add	r2, r7, #10
 976 0576 07F10B01 		add	r1, r7, #11
 977 057a FB88     		ldrh	r3, [r7, #6]
 978 057c 1846     		mov	r0, r3
 979 057e FFF773FD 		bl	gpio_port_pin_resolution
 247:srcc/gpio.c   **** 
 248:srcc/gpio.c   **** 	if(port >= 10)
 980              		.loc 2 248 0
 981 0582 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 982 0584 092B     		cmp	r3, #9
 983 0586 2CD9     		bls	.L49
 249:srcc/gpio.c   **** 	{
 250:srcc/gpio.c   **** 		gpio_not_ptr = (DIO_PORT_Not_Interruptable_Type*)PJ;
 984              		.loc 2 250 0
 985 0588 4E4B     		ldr	r3, .L58
 986 058a FB60     		str	r3, [r7, #12]
 251:srcc/gpio.c   **** 		if(BGET(pin,gpio_not_ptr->OUT))       //»ñÈ¡µ±Ç°Êä³öµçÆ½¸ßµÍ
 987              		.loc 2 251 0
 988 058c FB68     		ldr	r3, [r7, #12]
 989 058e 5B88     		ldrh	r3, [r3, #2]	@ movhi
 990 0590 9BB2     		uxth	r3, r3
 991 0592 1A46     		mov	r2, r3
 992 0594 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 993 0596 42FA03F3 		asr	r3, r2, r3
 994 059a 03F00103 		and	r3, r3, #1
 995 059e 002B     		cmp	r3, #0
 996 05a0 10D0     		beq	.L50
 252:srcc/gpio.c   **** 		{
 253:srcc/gpio.c   **** 			BCLR(pin,gpio_not_ptr->OUT);      //ÉèÖÃÊä³öµÍµçÆ½
 997              		.loc 2 253 0
 998 05a2 FB68     		ldr	r3, [r7, #12]
 999 05a4 5B88     		ldrh	r3, [r3, #2]	@ movhi
 1000 05a6 9BB2     		uxth	r3, r3
 1001 05a8 1AB2     		sxth	r2, r3
 1002 05aa BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1003 05ac 1946     		mov	r1, r3
 1004 05ae 0123     		movs	r3, #1
 1005 05b0 8B40     		lsls	r3, r3, r1
 1006 05b2 1BB2     		sxth	r3, r3
 1007 05b4 DB43     		mvns	r3, r3
 1008 05b6 1BB2     		sxth	r3, r3
 1009 05b8 1340     		ands	r3, r3, r2
 1010 05ba 1BB2     		sxth	r3, r3
 1011 05bc 9AB2     		uxth	r2, r3
 1012 05be FB68     		ldr	r3, [r7, #12]
 1013 05c0 5A80     		strh	r2, [r3, #2]	@ movhi
 254:srcc/gpio.c   **** 		}
 255:srcc/gpio.c   **** 		else
 256:srcc/gpio.c   **** 		{
 257:srcc/gpio.c   **** 			BSET(pin,gpio_not_ptr->OUT);      //ÉèÖÃÊä³ö¸ßµçÆ½
 258:srcc/gpio.c   **** 		}
 259:srcc/gpio.c   **** 	}
 260:srcc/gpio.c   **** 	else if(port%2 == 0)
 261:srcc/gpio.c   **** 	{
 262:srcc/gpio.c   **** 		gpio_odd_ptr =(DIO_PORT_Odd_Interruptable_Type*) (GPIO_ODD_ARR[port/2]);
 263:srcc/gpio.c   **** 		if(BGET(pin,gpio_odd_ptr->OUT))       //»ñÈ¡µ±Ç°Êä³öµçÆ½¸ßµÍ
 264:srcc/gpio.c   **** 		{
 265:srcc/gpio.c   **** 			BCLR(pin,gpio_odd_ptr->OUT);      //ÉèÖÃÊä³öµÍµçÆ½
 266:srcc/gpio.c   **** 		}
 267:srcc/gpio.c   **** 		else
 268:srcc/gpio.c   **** 		{
 269:srcc/gpio.c   **** 			BSET(pin,gpio_odd_ptr->OUT);      //ÉèÖÃÊä³ö¸ßµçÆ½
 270:srcc/gpio.c   **** 		}
 271:srcc/gpio.c   **** 	}
 272:srcc/gpio.c   **** 	else
 273:srcc/gpio.c   **** 	{
 274:srcc/gpio.c   **** 		gpio_even_ptr =(DIO_PORT_Even_Interruptable_Type*) (GPIO_EVEN_ARR[(port-1)/2]);
 275:srcc/gpio.c   **** 		if(BGET(pin,gpio_even_ptr->OUT))       //»ñÈ¡µ±Ç°Êä³öµçÆ½¸ßµÍ
 276:srcc/gpio.c   **** 		{
 277:srcc/gpio.c   **** 			BCLR(pin,gpio_even_ptr->OUT);      //ÉèÖÃÊä³öµÍµçÆ½
 278:srcc/gpio.c   **** 		}
 279:srcc/gpio.c   **** 		else
 280:srcc/gpio.c   **** 		{
 281:srcc/gpio.c   **** 			BSET(pin,gpio_even_ptr->OUT);      //ÉèÖÃÊä³ö¸ßµçÆ½
 282:srcc/gpio.c   **** 		}
 283:srcc/gpio.c   **** 	}
 284:srcc/gpio.c   **** }
 1014              		.loc 2 284 0
 1015 05c2 7BE0     		b	.L57
 1016              	.L50:
 257:srcc/gpio.c   **** 		}
 1017              		.loc 2 257 0
 1018 05c4 FB68     		ldr	r3, [r7, #12]
 1019 05c6 5B88     		ldrh	r3, [r3, #2]	@ movhi
 1020 05c8 9BB2     		uxth	r3, r3
 1021 05ca 1AB2     		sxth	r2, r3
 1022 05cc BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1023 05ce 1946     		mov	r1, r3
 1024 05d0 0123     		movs	r3, #1
 1025 05d2 8B40     		lsls	r3, r3, r1
 1026 05d4 1BB2     		sxth	r3, r3
 1027 05d6 1343     		orrs	r3, r3, r2
 1028 05d8 1BB2     		sxth	r3, r3
 1029 05da 9AB2     		uxth	r2, r3
 1030 05dc FB68     		ldr	r3, [r7, #12]
 1031 05de 5A80     		strh	r2, [r3, #2]	@ movhi
 1032              		.loc 2 284 0
 1033 05e0 6CE0     		b	.L57
 1034              	.L49:
 260:srcc/gpio.c   **** 	{
 1035              		.loc 2 260 0
 1036 05e2 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1037 05e4 03F00103 		and	r3, r3, #1
 1038 05e8 DBB2     		uxtb	r3, r3
 1039 05ea 002B     		cmp	r3, #0
 1040 05ec 32D1     		bne	.L53
 262:srcc/gpio.c   **** 		if(BGET(pin,gpio_odd_ptr->OUT))       //»ñÈ¡µ±Ç°Êä³öµçÆ½¸ßµÍ
 1041              		.loc 2 262 0
 1042 05ee FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1043 05f0 5B08     		lsrs	r3, r3, #1
 1044 05f2 DBB2     		uxtb	r3, r3
 1045 05f4 1A46     		mov	r2, r3
 1046 05f6 344B     		ldr	r3, .L58+4
 1047 05f8 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1048 05fc 3B61     		str	r3, [r7, #16]
 263:srcc/gpio.c   **** 		{
 1049              		.loc 2 263 0
 1050 05fe 3B69     		ldr	r3, [r7, #16]
 1051 0600 9B78     		ldrb	r3, [r3, #2]
 1052 0602 DBB2     		uxtb	r3, r3
 1053 0604 1A46     		mov	r2, r3
 1054 0606 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1055 0608 42FA03F3 		asr	r3, r2, r3
 1056 060c 03F00103 		and	r3, r3, #1
 1057 0610 002B     		cmp	r3, #0
 1058 0612 10D0     		beq	.L54
 265:srcc/gpio.c   **** 		}
 1059              		.loc 2 265 0
 1060 0614 3B69     		ldr	r3, [r7, #16]
 1061 0616 9B78     		ldrb	r3, [r3, #2]
 1062 0618 DBB2     		uxtb	r3, r3
 1063 061a 5AB2     		sxtb	r2, r3
 1064 061c BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1065 061e 1946     		mov	r1, r3
 1066 0620 0123     		movs	r3, #1
 1067 0622 8B40     		lsls	r3, r3, r1
 1068 0624 5BB2     		sxtb	r3, r3
 1069 0626 DB43     		mvns	r3, r3
 1070 0628 5BB2     		sxtb	r3, r3
 1071 062a 1340     		ands	r3, r3, r2
 1072 062c 5BB2     		sxtb	r3, r3
 1073 062e DAB2     		uxtb	r2, r3
 1074 0630 3B69     		ldr	r3, [r7, #16]
 1075 0632 9A70     		strb	r2, [r3, #2]
 1076              		.loc 2 284 0
 1077 0634 42E0     		b	.L57
 1078              	.L54:
 269:srcc/gpio.c   **** 		}
 1079              		.loc 2 269 0
 1080 0636 3B69     		ldr	r3, [r7, #16]
 1081 0638 9B78     		ldrb	r3, [r3, #2]
 1082 063a DBB2     		uxtb	r3, r3
 1083 063c 5AB2     		sxtb	r2, r3
 1084 063e BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1085 0640 1946     		mov	r1, r3
 1086 0642 0123     		movs	r3, #1
 1087 0644 8B40     		lsls	r3, r3, r1
 1088 0646 5BB2     		sxtb	r3, r3
 1089 0648 1343     		orrs	r3, r3, r2
 1090 064a 5BB2     		sxtb	r3, r3
 1091 064c DAB2     		uxtb	r2, r3
 1092 064e 3B69     		ldr	r3, [r7, #16]
 1093 0650 9A70     		strb	r2, [r3, #2]
 1094              		.loc 2 284 0
 1095 0652 33E0     		b	.L57
 1096              	.L53:
 274:srcc/gpio.c   **** 		if(BGET(pin,gpio_even_ptr->OUT))       //»ñÈ¡µ±Ç°Êä³öµçÆ½¸ßµÍ
 1097              		.loc 2 274 0
 1098 0654 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1099 0656 013B     		subs	r3, r3, #1
 1100 0658 DA0F     		lsrs	r2, r3, #31
 1101 065a 1344     		add	r3, r3, r2
 1102 065c 5B10     		asrs	r3, r3, #1
 1103 065e 1A46     		mov	r2, r3
 1104 0660 1A4B     		ldr	r3, .L58+8
 1105 0662 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1106 0666 7B61     		str	r3, [r7, #20]
 275:srcc/gpio.c   **** 		{
 1107              		.loc 2 275 0
 1108 0668 7B69     		ldr	r3, [r7, #20]
 1109 066a DB78     		ldrb	r3, [r3, #3]
 1110 066c DBB2     		uxtb	r3, r3
 1111 066e 1A46     		mov	r2, r3
 1112 0670 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1113 0672 42FA03F3 		asr	r3, r2, r3
 1114 0676 03F00103 		and	r3, r3, #1
 1115 067a 002B     		cmp	r3, #0
 1116 067c 10D0     		beq	.L56
 277:srcc/gpio.c   **** 		}
 1117              		.loc 2 277 0
 1118 067e 7B69     		ldr	r3, [r7, #20]
 1119 0680 DB78     		ldrb	r3, [r3, #3]
 1120 0682 DBB2     		uxtb	r3, r3
 1121 0684 5AB2     		sxtb	r2, r3
 1122 0686 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1123 0688 1946     		mov	r1, r3
 1124 068a 0123     		movs	r3, #1
 1125 068c 8B40     		lsls	r3, r3, r1
 1126 068e 5BB2     		sxtb	r3, r3
 1127 0690 DB43     		mvns	r3, r3
 1128 0692 5BB2     		sxtb	r3, r3
 1129 0694 1340     		ands	r3, r3, r2
 1130 0696 5BB2     		sxtb	r3, r3
 1131 0698 DAB2     		uxtb	r2, r3
 1132 069a 7B69     		ldr	r3, [r7, #20]
 1133 069c DA70     		strb	r2, [r3, #3]
 1134              		.loc 2 284 0
 1135 069e 0DE0     		b	.L57
 1136              	.L56:
 281:srcc/gpio.c   **** 		}
 1137              		.loc 2 281 0
 1138 06a0 7B69     		ldr	r3, [r7, #20]
 1139 06a2 DB78     		ldrb	r3, [r3, #3]
 1140 06a4 DBB2     		uxtb	r3, r3
 1141 06a6 5AB2     		sxtb	r2, r3
 1142 06a8 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1143 06aa 1946     		mov	r1, r3
 1144 06ac 0123     		movs	r3, #1
 1145 06ae 8B40     		lsls	r3, r3, r1
 1146 06b0 5BB2     		sxtb	r3, r3
 1147 06b2 1343     		orrs	r3, r3, r2
 1148 06b4 5BB2     		sxtb	r3, r3
 1149 06b6 DAB2     		uxtb	r2, r3
 1150 06b8 7B69     		ldr	r3, [r7, #20]
 1151 06ba DA70     		strb	r2, [r3, #3]
 1152              	.L57:
 1153              		.loc 2 284 0
 1154 06bc 00BF     		nop
 1155 06be 1837     		adds	r7, r7, #24
 1156              		.cfi_def_cfa_offset 8
 1157 06c0 BD46     		mov	sp, r7
 1158              		.cfi_def_cfa_register 13
 1159              		@ sp needed
 1160 06c2 80BD     		pop	{r7, pc}
 1161              	.L59:
 1162              		.align	2
 1163              	.L58:
 1164 06c4 204D0040 		.word	1073761568
 1165 06c8 00000000 		.word	GPIO_ODD_ARR
 1166 06cc 00000000 		.word	GPIO_EVEN_ARR
 1167              		.cfi_endproc
 1168              	.LFE127:
 1170              		.align	1
 1171              		.global	gpio_pull
 1172              		.syntax unified
 1173              		.thumb
 1174              		.thumb_func
 1175              		.fpu fpv4-sp-d16
 1177              	gpio_pull:
 1178              	.LFB128:
 285:srcc/gpio.c   **** 
 286:srcc/gpio.c   **** //===========================================================================
 287:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_pull
 288:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
 289:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º¶Ë¿ÚºÅ|Òý½ÅºÅ (PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
 290:srcc/gpio.c   **** //         pullselect£ºÒý½ÅÀ­¸ßµÍµçÆ½£¨ 0=À­µÍµçÆ½£¬1=À­¸ßµçÆ½£©
 291:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£ºÊ¹Ö¸¶¨Òý½ÅÉÏÀ­¸ßµçÆ½»òÏÂÀ­µÍµçÆ½
 292:srcc/gpio.c   **** //===========================================================================
 293:srcc/gpio.c   **** void gpio_pull(uint16_t port_pin, uint8_t pullselect)
 294:srcc/gpio.c   **** {
 1179              		.loc 2 294 0
 1180              		.cfi_startproc
 1181              		@ args = 0, pretend = 0, frame = 24
 1182              		@ frame_needed = 1, uses_anonymous_args = 0
 1183 06d0 80B5     		push	{r7, lr}
 1184              		.cfi_def_cfa_offset 8
 1185              		.cfi_offset 7, -8
 1186              		.cfi_offset 14, -4
 1187 06d2 86B0     		sub	sp, sp, #24
 1188              		.cfi_def_cfa_offset 32
 1189 06d4 00AF     		add	r7, sp, #0
 1190              		.cfi_def_cfa_register 7
 1191 06d6 0346     		mov	r3, r0
 1192 06d8 0A46     		mov	r2, r1
 1193 06da FB80     		strh	r3, [r7, #6]	@ movhi
 1194 06dc 1346     		mov	r3, r2
 1195 06de 7B71     		strb	r3, [r7, #5]
 295:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
 296:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
 297:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
 298:srcc/gpio.c   **** 	DIO_PORT_Not_Interruptable_Type* gpio_not_ptr;
 299:srcc/gpio.c   **** 	uint8_t port;
 300:srcc/gpio.c   **** 	uint8_t pin;
 301:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 1196              		.loc 2 301 0
 1197 06e0 07F10A02 		add	r2, r7, #10
 1198 06e4 07F10B01 		add	r1, r7, #11
 1199 06e8 FB88     		ldrh	r3, [r7, #6]
 1200 06ea 1846     		mov	r0, r3
 1201 06ec FFF7BCFC 		bl	gpio_port_pin_resolution
 302:srcc/gpio.c   **** 
 303:srcc/gpio.c   **** 	if(port >= 10)
 1202              		.loc 2 303 0
 1203 06f0 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1204 06f2 092B     		cmp	r3, #9
 1205 06f4 24D9     		bls	.L61
 304:srcc/gpio.c   **** 	{
 305:srcc/gpio.c   **** 		gpio_not_ptr = (DIO_PORT_Not_Interruptable_Type*)PJ;
 1206              		.loc 2 305 0
 1207 06f6 434B     		ldr	r3, .L70
 1208 06f8 FB60     		str	r3, [r7, #12]
 306:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýpullselect£¬¾ö¶¨Òý½ÅÀ­¸ß»¹ÊÇÀ­µÍ
 307:srcc/gpio.c   **** 		if (1==pullselect)
 1209              		.loc 2 307 0
 1210 06fa 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 1211 06fc 012B     		cmp	r3, #1
 1212 06fe 0ED1     		bne	.L62
 308:srcc/gpio.c   **** 		{
 309:srcc/gpio.c   **** 			BSET(pin,gpio_not_ptr->REN);   //ÉèÖÃÇý¶¯ÄÜÁ¦
 1213              		.loc 2 309 0
 1214 0700 FB68     		ldr	r3, [r7, #12]
 1215 0702 DB88     		ldrh	r3, [r3, #6]	@ movhi
 1216 0704 9BB2     		uxth	r3, r3
 1217 0706 1AB2     		sxth	r2, r3
 1218 0708 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1219 070a 1946     		mov	r1, r3
 1220 070c 0123     		movs	r3, #1
 1221 070e 8B40     		lsls	r3, r3, r1
 1222 0710 1BB2     		sxth	r3, r3
 1223 0712 1343     		orrs	r3, r3, r2
 1224 0714 1BB2     		sxth	r3, r3
 1225 0716 9AB2     		uxth	r2, r3
 1226 0718 FB68     		ldr	r3, [r7, #12]
 1227 071a DA80     		strh	r2, [r3, #6]	@ movhi
 310:srcc/gpio.c   **** 		}
 311:srcc/gpio.c   **** 		else
 312:srcc/gpio.c   **** 		{
 313:srcc/gpio.c   **** 			BCLR(pin,gpio_not_ptr->REN);
 314:srcc/gpio.c   **** 		}
 315:srcc/gpio.c   **** 	}
 316:srcc/gpio.c   **** 	else if(port%2 == 0)
 317:srcc/gpio.c   **** 	{
 318:srcc/gpio.c   **** 		gpio_odd_ptr = (DIO_PORT_Odd_Interruptable_Type*) (GPIO_ODD_ARR[port/2]);
 319:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýpullselect£¬¾ö¶¨Òý½ÅÀ­¸ß»¹ÊÇÀ­µÍ
 320:srcc/gpio.c   **** 		if (1==pullselect)
 321:srcc/gpio.c   **** 		{
 322:srcc/gpio.c   **** 			BSET(pin,gpio_odd_ptr->REN);
 323:srcc/gpio.c   **** 		}
 324:srcc/gpio.c   **** 		else
 325:srcc/gpio.c   **** 		{
 326:srcc/gpio.c   **** 			BCLR(pin,gpio_odd_ptr->REN);
 327:srcc/gpio.c   **** 		}
 328:srcc/gpio.c   **** 	}
 329:srcc/gpio.c   **** 	else
 330:srcc/gpio.c   **** 	{
 331:srcc/gpio.c   **** 		gpio_even_ptr = (DIO_PORT_Even_Interruptable_Type*) (GPIO_EVEN_ARR[(port-1)/2]);
 332:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýpullselect£¬¾ö¶¨Òý½ÅÀ­¸ß»¹ÊÇÀ­µÍ
 333:srcc/gpio.c   **** 		if (1==pullselect)
 334:srcc/gpio.c   **** 		{
 335:srcc/gpio.c   **** 			BSET(pin,gpio_even_ptr->REN);
 336:srcc/gpio.c   **** 		}
 337:srcc/gpio.c   **** 		else
 338:srcc/gpio.c   **** 		{
 339:srcc/gpio.c   **** 			BCLR(pin,gpio_even_ptr->REN);
 340:srcc/gpio.c   **** 		}
 341:srcc/gpio.c   **** 	}
 342:srcc/gpio.c   **** }
 1228              		.loc 2 342 0
 1229 071c 6DE0     		b	.L69
 1230              	.L62:
 313:srcc/gpio.c   **** 		}
 1231              		.loc 2 313 0
 1232 071e FB68     		ldr	r3, [r7, #12]
 1233 0720 DB88     		ldrh	r3, [r3, #6]	@ movhi
 1234 0722 9BB2     		uxth	r3, r3
 1235 0724 1AB2     		sxth	r2, r3
 1236 0726 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1237 0728 1946     		mov	r1, r3
 1238 072a 0123     		movs	r3, #1
 1239 072c 8B40     		lsls	r3, r3, r1
 1240 072e 1BB2     		sxth	r3, r3
 1241 0730 DB43     		mvns	r3, r3
 1242 0732 1BB2     		sxth	r3, r3
 1243 0734 1340     		ands	r3, r3, r2
 1244 0736 1BB2     		sxth	r3, r3
 1245 0738 9AB2     		uxth	r2, r3
 1246 073a FB68     		ldr	r3, [r7, #12]
 1247 073c DA80     		strh	r2, [r3, #6]	@ movhi
 1248              		.loc 2 342 0
 1249 073e 5CE0     		b	.L69
 1250              	.L61:
 316:srcc/gpio.c   **** 	{
 1251              		.loc 2 316 0
 1252 0740 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1253 0742 03F00103 		and	r3, r3, #1
 1254 0746 DBB2     		uxtb	r3, r3
 1255 0748 002B     		cmp	r3, #0
 1256 074a 2AD1     		bne	.L65
 318:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýpullselect£¬¾ö¶¨Òý½ÅÀ­¸ß»¹ÊÇÀ­µÍ
 1257              		.loc 2 318 0
 1258 074c FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1259 074e 5B08     		lsrs	r3, r3, #1
 1260 0750 DBB2     		uxtb	r3, r3
 1261 0752 1A46     		mov	r2, r3
 1262 0754 2C4B     		ldr	r3, .L70+4
 1263 0756 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1264 075a 3B61     		str	r3, [r7, #16]
 320:srcc/gpio.c   **** 		{
 1265              		.loc 2 320 0
 1266 075c 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 1267 075e 012B     		cmp	r3, #1
 1268 0760 0ED1     		bne	.L66
 322:srcc/gpio.c   **** 		}
 1269              		.loc 2 322 0
 1270 0762 3B69     		ldr	r3, [r7, #16]
 1271 0764 9B79     		ldrb	r3, [r3, #6]
 1272 0766 DBB2     		uxtb	r3, r3
 1273 0768 5AB2     		sxtb	r2, r3
 1274 076a BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1275 076c 1946     		mov	r1, r3
 1276 076e 0123     		movs	r3, #1
 1277 0770 8B40     		lsls	r3, r3, r1
 1278 0772 5BB2     		sxtb	r3, r3
 1279 0774 1343     		orrs	r3, r3, r2
 1280 0776 5BB2     		sxtb	r3, r3
 1281 0778 DAB2     		uxtb	r2, r3
 1282 077a 3B69     		ldr	r3, [r7, #16]
 1283 077c 9A71     		strb	r2, [r3, #6]
 1284              		.loc 2 342 0
 1285 077e 3CE0     		b	.L69
 1286              	.L66:
 326:srcc/gpio.c   **** 		}
 1287              		.loc 2 326 0
 1288 0780 3B69     		ldr	r3, [r7, #16]
 1289 0782 9B79     		ldrb	r3, [r3, #6]
 1290 0784 DBB2     		uxtb	r3, r3
 1291 0786 5AB2     		sxtb	r2, r3
 1292 0788 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1293 078a 1946     		mov	r1, r3
 1294 078c 0123     		movs	r3, #1
 1295 078e 8B40     		lsls	r3, r3, r1
 1296 0790 5BB2     		sxtb	r3, r3
 1297 0792 DB43     		mvns	r3, r3
 1298 0794 5BB2     		sxtb	r3, r3
 1299 0796 1340     		ands	r3, r3, r2
 1300 0798 5BB2     		sxtb	r3, r3
 1301 079a DAB2     		uxtb	r2, r3
 1302 079c 3B69     		ldr	r3, [r7, #16]
 1303 079e 9A71     		strb	r2, [r3, #6]
 1304              		.loc 2 342 0
 1305 07a0 2BE0     		b	.L69
 1306              	.L65:
 331:srcc/gpio.c   **** 		//¸ù¾Ý´øÈë²ÎÊýpullselect£¬¾ö¶¨Òý½ÅÀ­¸ß»¹ÊÇÀ­µÍ
 1307              		.loc 2 331 0
 1308 07a2 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1309 07a4 013B     		subs	r3, r3, #1
 1310 07a6 DA0F     		lsrs	r2, r3, #31
 1311 07a8 1344     		add	r3, r3, r2
 1312 07aa 5B10     		asrs	r3, r3, #1
 1313 07ac 1A46     		mov	r2, r3
 1314 07ae 174B     		ldr	r3, .L70+8
 1315 07b0 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1316 07b4 7B61     		str	r3, [r7, #20]
 333:srcc/gpio.c   **** 		{
 1317              		.loc 2 333 0
 1318 07b6 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 1319 07b8 012B     		cmp	r3, #1
 1320 07ba 0ED1     		bne	.L68
 335:srcc/gpio.c   **** 		}
 1321              		.loc 2 335 0
 1322 07bc 7B69     		ldr	r3, [r7, #20]
 1323 07be DB79     		ldrb	r3, [r3, #7]
 1324 07c0 DBB2     		uxtb	r3, r3
 1325 07c2 5AB2     		sxtb	r2, r3
 1326 07c4 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1327 07c6 1946     		mov	r1, r3
 1328 07c8 0123     		movs	r3, #1
 1329 07ca 8B40     		lsls	r3, r3, r1
 1330 07cc 5BB2     		sxtb	r3, r3
 1331 07ce 1343     		orrs	r3, r3, r2
 1332 07d0 5BB2     		sxtb	r3, r3
 1333 07d2 DAB2     		uxtb	r2, r3
 1334 07d4 7B69     		ldr	r3, [r7, #20]
 1335 07d6 DA71     		strb	r2, [r3, #7]
 1336              		.loc 2 342 0
 1337 07d8 0FE0     		b	.L69
 1338              	.L68:
 339:srcc/gpio.c   **** 		}
 1339              		.loc 2 339 0
 1340 07da 7B69     		ldr	r3, [r7, #20]
 1341 07dc DB79     		ldrb	r3, [r3, #7]
 1342 07de DBB2     		uxtb	r3, r3
 1343 07e0 5AB2     		sxtb	r2, r3
 1344 07e2 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1345 07e4 1946     		mov	r1, r3
 1346 07e6 0123     		movs	r3, #1
 1347 07e8 8B40     		lsls	r3, r3, r1
 1348 07ea 5BB2     		sxtb	r3, r3
 1349 07ec DB43     		mvns	r3, r3
 1350 07ee 5BB2     		sxtb	r3, r3
 1351 07f0 1340     		ands	r3, r3, r2
 1352 07f2 5BB2     		sxtb	r3, r3
 1353 07f4 DAB2     		uxtb	r2, r3
 1354 07f6 7B69     		ldr	r3, [r7, #20]
 1355 07f8 DA71     		strb	r2, [r3, #7]
 1356              	.L69:
 1357              		.loc 2 342 0
 1358 07fa 00BF     		nop
 1359 07fc 1837     		adds	r7, r7, #24
 1360              		.cfi_def_cfa_offset 8
 1361 07fe BD46     		mov	sp, r7
 1362              		.cfi_def_cfa_register 13
 1363              		@ sp needed
 1364 0800 80BD     		pop	{r7, pc}
 1365              	.L71:
 1366 0802 00BF     		.align	2
 1367              	.L70:
 1368 0804 204D0040 		.word	1073761568
 1369 0808 00000000 		.word	GPIO_ODD_ARR
 1370 080c 00000000 		.word	GPIO_EVEN_ARR
 1371              		.cfi_endproc
 1372              	.LFE128:
 1374              		.align	1
 1375              		.global	gpio_enable_int
 1376              		.syntax unified
 1377              		.thumb
 1378              		.thumb_func
 1379              		.fpu fpv4-sp-d16
 1381              	gpio_enable_int:
 1382              	.LFB129:
 343:srcc/gpio.c   **** 
 344:srcc/gpio.c   **** //===========================================================================
 345:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_enable_int
 346:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
 347:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º(¶Ë¿ÚºÅ)|(Òý½ÅºÅ)(PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
 348:srcc/gpio.c   **** //          irqtype£ºÒý½ÅÖÐ¶ÏÀàÐÍ£¬ÓÉºê¶¨Òå¸ø³ö£¬ÔÙ´ÎÁÐ¾ÙÈçÏÂ£º
 349:srcc/gpio.c   **** //                  RISING_EDGE  0      //ÉÏÉýÑØ´¥·¢
 350:srcc/gpio.c   **** //                  FALLING_EDGE 1     //ÏÂ½µÑØ´¥·¢
 351:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£ºµ±Ö¸¶¨¶Ë¿ÚÒý½Å±»¶¨ÒåÎªGPIO¹¦ÄÜÇÒÎªÊäÈëÊ±£¬±¾º¯Êý¿ªÆôÒý½ÅÖÐ¶Ï£¬²¢
 352:srcc/gpio.c   **** //          ÉèÖÃÖÐ¶Ï´¥·¢Ìõ¼þ¡£
 353:srcc/gpio.c   **** //×¢          Òâ£º MP432P401RÐ¾Æ¬£¬Ö»ÓÐPORT1~PORT6¿Ú¾ßÓÐGPIOÀàÖÐ¶Ï¹¦ÄÜ
 354:srcc/gpio.c   **** //
 355:srcc/gpio.c   **** //===========================================================================
 356:srcc/gpio.c   **** void gpio_enable_int(uint16_t port_pin,uint8_t irqtype)
 357:srcc/gpio.c   **** {
 1383              		.loc 2 357 0
 1384              		.cfi_startproc
 1385              		@ args = 0, pretend = 0, frame = 24
 1386              		@ frame_needed = 1, uses_anonymous_args = 0
 1387 0810 80B5     		push	{r7, lr}
 1388              		.cfi_def_cfa_offset 8
 1389              		.cfi_offset 7, -8
 1390              		.cfi_offset 14, -4
 1391 0812 86B0     		sub	sp, sp, #24
 1392              		.cfi_def_cfa_offset 32
 1393 0814 00AF     		add	r7, sp, #0
 1394              		.cfi_def_cfa_register 7
 1395 0816 0346     		mov	r3, r0
 1396 0818 0A46     		mov	r2, r1
 1397 081a FB80     		strh	r3, [r7, #6]	@ movhi
 1398 081c 1346     		mov	r3, r2
 1399 081e 7B71     		strb	r3, [r7, #5]
 358:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
 359:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
 360:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
 361:srcc/gpio.c   **** 	uint8_t port;
 362:srcc/gpio.c   **** 	uint8_t pin;
 363:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 1400              		.loc 2 363 0
 1401 0820 07F10E02 		add	r2, r7, #14
 1402 0824 07F10F01 		add	r1, r7, #15
 1403 0828 FB88     		ldrh	r3, [r7, #6]
 1404 082a 1846     		mov	r0, r3
 1405 082c FFF71CFC 		bl	gpio_port_pin_resolution
 364:srcc/gpio.c   **** 
 365:srcc/gpio.c   **** 	if(port%2 == 0)
 1406              		.loc 2 365 0
 1407 0830 FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1408 0832 03F00103 		and	r3, r3, #1
 1409 0836 DBB2     		uxtb	r3, r3
 1410 0838 002B     		cmp	r3, #0
 1411 083a 48D1     		bne	.L73
 366:srcc/gpio.c   **** 	{
 367:srcc/gpio.c   **** 		gpio_odd_ptr = (DIO_PORT_Odd_Interruptable_Type*) (GPIO_ODD_ARR[port/2]);
 1412              		.loc 2 367 0
 1413 083c FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1414 083e 5B08     		lsrs	r3, r3, #1
 1415 0840 DBB2     		uxtb	r3, r3
 1416 0842 1A46     		mov	r2, r3
 1417 0844 5E4B     		ldr	r3, .L88
 1418 0846 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1419 084a 3B61     		str	r3, [r7, #16]
 368:srcc/gpio.c   **** 		BCLR(pin,gpio_odd_ptr->IFG);         //Çå³ýÒý½ÅÖÐ¶Ï±êÖ¾
 1420              		.loc 2 368 0
 1421 084c 3B69     		ldr	r3, [r7, #16]
 1422 084e 1B7F     		ldrb	r3, [r3, #28]
 1423 0850 DBB2     		uxtb	r3, r3
 1424 0852 5AB2     		sxtb	r2, r3
 1425 0854 BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1426 0856 1946     		mov	r1, r3
 1427 0858 0123     		movs	r3, #1
 1428 085a 8B40     		lsls	r3, r3, r1
 1429 085c 5BB2     		sxtb	r3, r3
 1430 085e DB43     		mvns	r3, r3
 1431 0860 5BB2     		sxtb	r3, r3
 1432 0862 1340     		ands	r3, r3, r2
 1433 0864 5BB2     		sxtb	r3, r3
 1434 0866 DAB2     		uxtb	r2, r3
 1435 0868 3B69     		ldr	r3, [r7, #16]
 1436 086a 1A77     		strb	r2, [r3, #28]
 369:srcc/gpio.c   **** 		if(irqtype == 1)
 1437              		.loc 2 369 0
 1438 086c 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 1439 086e 012B     		cmp	r3, #1
 1440 0870 0ED1     		bne	.L74
 370:srcc/gpio.c   **** 		{
 371:srcc/gpio.c   **** 			BSET(pin,gpio_odd_ptr->IES);	 //ÉèÖÃÉÏÉýÑØÖÐ¶Ï»òÕßÏÂ½µÑØÖÐ¶Ï
 1441              		.loc 2 371 0
 1442 0872 3B69     		ldr	r3, [r7, #16]
 1443 0874 1B7E     		ldrb	r3, [r3, #24]
 1444 0876 DBB2     		uxtb	r3, r3
 1445 0878 5AB2     		sxtb	r2, r3
 1446 087a BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1447 087c 1946     		mov	r1, r3
 1448 087e 0123     		movs	r3, #1
 1449 0880 8B40     		lsls	r3, r3, r1
 1450 0882 5BB2     		sxtb	r3, r3
 1451 0884 1343     		orrs	r3, r3, r2
 1452 0886 5BB2     		sxtb	r3, r3
 1453 0888 DAB2     		uxtb	r2, r3
 1454 088a 3B69     		ldr	r3, [r7, #16]
 1455 088c 1A76     		strb	r2, [r3, #24]
 1456 088e 0FE0     		b	.L75
 1457              	.L74:
 372:srcc/gpio.c   **** 		}
 373:srcc/gpio.c   **** 		else
 374:srcc/gpio.c   **** 		{
 375:srcc/gpio.c   **** 			BCLR(pin,gpio_odd_ptr->IES);	 //ÉèÖÃÉÏÉýÑØÖÐ¶Ï»òÕßÏÂ½µÑØÖÐ¶Ï
 1458              		.loc 2 375 0
 1459 0890 3B69     		ldr	r3, [r7, #16]
 1460 0892 1B7E     		ldrb	r3, [r3, #24]
 1461 0894 DBB2     		uxtb	r3, r3
 1462 0896 5AB2     		sxtb	r2, r3
 1463 0898 BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1464 089a 1946     		mov	r1, r3
 1465 089c 0123     		movs	r3, #1
 1466 089e 8B40     		lsls	r3, r3, r1
 1467 08a0 5BB2     		sxtb	r3, r3
 1468 08a2 DB43     		mvns	r3, r3
 1469 08a4 5BB2     		sxtb	r3, r3
 1470 08a6 1340     		ands	r3, r3, r2
 1471 08a8 5BB2     		sxtb	r3, r3
 1472 08aa DAB2     		uxtb	r2, r3
 1473 08ac 3B69     		ldr	r3, [r7, #16]
 1474 08ae 1A76     		strb	r2, [r3, #24]
 1475              	.L75:
 376:srcc/gpio.c   **** 		}
 377:srcc/gpio.c   **** 	    BSET(pin,gpio_odd_ptr->IE);          //Ê¹ÄÜÒý½ÅÖÐ¶Ï
 1476              		.loc 2 377 0
 1477 08b0 3B69     		ldr	r3, [r7, #16]
 1478 08b2 9B7E     		ldrb	r3, [r3, #26]
 1479 08b4 DBB2     		uxtb	r3, r3
 1480 08b6 5AB2     		sxtb	r2, r3
 1481 08b8 BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1482 08ba 1946     		mov	r1, r3
 1483 08bc 0123     		movs	r3, #1
 1484 08be 8B40     		lsls	r3, r3, r1
 1485 08c0 5BB2     		sxtb	r3, r3
 1486 08c2 1343     		orrs	r3, r3, r2
 1487 08c4 5BB2     		sxtb	r3, r3
 1488 08c6 DAB2     		uxtb	r2, r3
 1489 08c8 3B69     		ldr	r3, [r7, #16]
 1490 08ca 9A76     		strb	r2, [r3, #26]
 1491 08cc 49E0     		b	.L76
 1492              	.L73:
 378:srcc/gpio.c   **** 	}
 379:srcc/gpio.c   **** 	else
 380:srcc/gpio.c   **** 	{
 381:srcc/gpio.c   **** 		gpio_even_ptr = (DIO_PORT_Even_Interruptable_Type*) (GPIO_EVEN_ARR[(port-1)/2]);
 1493              		.loc 2 381 0
 1494 08ce FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1495 08d0 013B     		subs	r3, r3, #1
 1496 08d2 DA0F     		lsrs	r2, r3, #31
 1497 08d4 1344     		add	r3, r3, r2
 1498 08d6 5B10     		asrs	r3, r3, #1
 1499 08d8 1A46     		mov	r2, r3
 1500 08da 3A4B     		ldr	r3, .L88+4
 1501 08dc 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1502 08e0 7B61     		str	r3, [r7, #20]
 382:srcc/gpio.c   **** 		BCLR(pin,gpio_even_ptr->IFG);        //Çå³ýÒý½ÅÖÐ¶Ï±êÖ¾
 1503              		.loc 2 382 0
 1504 08e2 7B69     		ldr	r3, [r7, #20]
 1505 08e4 5B7F     		ldrb	r3, [r3, #29]
 1506 08e6 DBB2     		uxtb	r3, r3
 1507 08e8 5AB2     		sxtb	r2, r3
 1508 08ea BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1509 08ec 1946     		mov	r1, r3
 1510 08ee 0123     		movs	r3, #1
 1511 08f0 8B40     		lsls	r3, r3, r1
 1512 08f2 5BB2     		sxtb	r3, r3
 1513 08f4 DB43     		mvns	r3, r3
 1514 08f6 5BB2     		sxtb	r3, r3
 1515 08f8 1340     		ands	r3, r3, r2
 1516 08fa 5BB2     		sxtb	r3, r3
 1517 08fc DAB2     		uxtb	r2, r3
 1518 08fe 7B69     		ldr	r3, [r7, #20]
 1519 0900 5A77     		strb	r2, [r3, #29]
 383:srcc/gpio.c   **** 		if(irqtype == 1)
 1520              		.loc 2 383 0
 1521 0902 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 1522 0904 012B     		cmp	r3, #1
 1523 0906 0ED1     		bne	.L77
 384:srcc/gpio.c   **** 		{
 385:srcc/gpio.c   **** 			BSET(pin,gpio_even_ptr->IES);	 //ÉèÖÃÉÏÉýÑØÖÐ¶Ï»òÕßÏÂ½µÑØÖÐ¶Ï
 1524              		.loc 2 385 0
 1525 0908 7B69     		ldr	r3, [r7, #20]
 1526 090a 5B7E     		ldrb	r3, [r3, #25]
 1527 090c DBB2     		uxtb	r3, r3
 1528 090e 5AB2     		sxtb	r2, r3
 1529 0910 BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1530 0912 1946     		mov	r1, r3
 1531 0914 0123     		movs	r3, #1
 1532 0916 8B40     		lsls	r3, r3, r1
 1533 0918 5BB2     		sxtb	r3, r3
 1534 091a 1343     		orrs	r3, r3, r2
 1535 091c 5BB2     		sxtb	r3, r3
 1536 091e DAB2     		uxtb	r2, r3
 1537 0920 7B69     		ldr	r3, [r7, #20]
 1538 0922 5A76     		strb	r2, [r3, #25]
 1539 0924 0FE0     		b	.L78
 1540              	.L77:
 386:srcc/gpio.c   **** 		}
 387:srcc/gpio.c   **** 		else
 388:srcc/gpio.c   **** 		{
 389:srcc/gpio.c   **** 			BCLR(pin,gpio_even_ptr->IES);	 //ÉèÖÃÉÏÉýÑØÖÐ¶Ï»òÕßÏÂ½µÑØÖÐ¶Ï
 1541              		.loc 2 389 0
 1542 0926 7B69     		ldr	r3, [r7, #20]
 1543 0928 5B7E     		ldrb	r3, [r3, #25]
 1544 092a DBB2     		uxtb	r3, r3
 1545 092c 5AB2     		sxtb	r2, r3
 1546 092e BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1547 0930 1946     		mov	r1, r3
 1548 0932 0123     		movs	r3, #1
 1549 0934 8B40     		lsls	r3, r3, r1
 1550 0936 5BB2     		sxtb	r3, r3
 1551 0938 DB43     		mvns	r3, r3
 1552 093a 5BB2     		sxtb	r3, r3
 1553 093c 1340     		ands	r3, r3, r2
 1554 093e 5BB2     		sxtb	r3, r3
 1555 0940 DAB2     		uxtb	r2, r3
 1556 0942 7B69     		ldr	r3, [r7, #20]
 1557 0944 5A76     		strb	r2, [r3, #25]
 1558              	.L78:
 390:srcc/gpio.c   **** 		}
 391:srcc/gpio.c   **** 	    BSET(pin,gpio_even_ptr->IE);         //Ê¹ÄÜÒý½ÅÖÐ¶Ï
 1559              		.loc 2 391 0
 1560 0946 7B69     		ldr	r3, [r7, #20]
 1561 0948 DB7E     		ldrb	r3, [r3, #27]
 1562 094a DBB2     		uxtb	r3, r3
 1563 094c 5AB2     		sxtb	r2, r3
 1564 094e BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1565 0950 1946     		mov	r1, r3
 1566 0952 0123     		movs	r3, #1
 1567 0954 8B40     		lsls	r3, r3, r1
 1568 0956 5BB2     		sxtb	r3, r3
 1569 0958 1343     		orrs	r3, r3, r2
 1570 095a 5BB2     		sxtb	r3, r3
 1571 095c DAB2     		uxtb	r2, r3
 1572 095e 7B69     		ldr	r3, [r7, #20]
 1573 0960 DA76     		strb	r2, [r3, #27]
 1574              	.L76:
 392:srcc/gpio.c   **** 	}
 393:srcc/gpio.c   **** 
 394:srcc/gpio.c   ****     switch(port)
 1575              		.loc 2 394 0
 1576 0962 FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1577 0964 052B     		cmp	r3, #5
 1578 0966 27D8     		bhi	.L87
 1579 0968 01A2     		adr	r2, .L81
 1580 096a 52F823F0 		ldr	pc, [r2, r3, lsl #2]
 1581 096e 00BF     		.p2align 2
 1582              	.L81:
 1583 0970 89090000 		.word	.L80+1
 1584 0974 91090000 		.word	.L82+1
 1585 0978 99090000 		.word	.L83+1
 1586 097c A1090000 		.word	.L84+1
 1587 0980 A9090000 		.word	.L85+1
 1588 0984 B1090000 		.word	.L86+1
 1589              		.p2align 1
 1590              	.L80:
 395:srcc/gpio.c   ****     {
 396:srcc/gpio.c   ****     case 0://PT1
 397:srcc/gpio.c   ****     	NVIC_EnableIRQ((IRQn_Type)35);     //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1591              		.loc 2 397 0
 1592 0988 2320     		movs	r0, #35
 1593 098a FFF739FB 		bl	NVIC_EnableIRQ
 398:srcc/gpio.c   ****     	break;
 1594              		.loc 2 398 0
 1595 098e 13E0     		b	.L79
 1596              	.L82:
 399:srcc/gpio.c   ****     case 1://PT2
 400:srcc/gpio.c   ****     	NVIC_EnableIRQ((IRQn_Type)36);     //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1597              		.loc 2 400 0
 1598 0990 2420     		movs	r0, #36
 1599 0992 FFF735FB 		bl	NVIC_EnableIRQ
 401:srcc/gpio.c   ****     	break;
 1600              		.loc 2 401 0
 1601 0996 0FE0     		b	.L79
 1602              	.L83:
 402:srcc/gpio.c   ****     case 2://PT3
 403:srcc/gpio.c   ****     	NVIC_EnableIRQ((IRQn_Type)37);     //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1603              		.loc 2 403 0
 1604 0998 2520     		movs	r0, #37
 1605 099a FFF731FB 		bl	NVIC_EnableIRQ
 404:srcc/gpio.c   ****         break;
 1606              		.loc 2 404 0
 1607 099e 0BE0     		b	.L79
 1608              	.L84:
 405:srcc/gpio.c   ****     case 3://PT4
 406:srcc/gpio.c   ****     	NVIC_EnableIRQ((IRQn_Type)38);     //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1609              		.loc 2 406 0
 1610 09a0 2620     		movs	r0, #38
 1611 09a2 FFF72DFB 		bl	NVIC_EnableIRQ
 407:srcc/gpio.c   ****         break;
 1612              		.loc 2 407 0
 1613 09a6 07E0     		b	.L79
 1614              	.L85:
 408:srcc/gpio.c   ****     case 4://PT5
 409:srcc/gpio.c   ****     	NVIC_EnableIRQ((IRQn_Type)39);     //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1615              		.loc 2 409 0
 1616 09a8 2720     		movs	r0, #39
 1617 09aa FFF729FB 		bl	NVIC_EnableIRQ
 410:srcc/gpio.c   ****         break;
 1618              		.loc 2 410 0
 1619 09ae 03E0     		b	.L79
 1620              	.L86:
 411:srcc/gpio.c   ****     case 5://PT6
 412:srcc/gpio.c   ****     	NVIC_EnableIRQ((IRQn_Type)40);     //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1621              		.loc 2 412 0
 1622 09b0 2820     		movs	r0, #40
 1623 09b2 FFF725FB 		bl	NVIC_EnableIRQ
 413:srcc/gpio.c   ****         break;
 1624              		.loc 2 413 0
 1625 09b6 00BF     		nop
 1626              	.L79:
 1627              	.L87:
 414:srcc/gpio.c   ****     default:;
 415:srcc/gpio.c   ****     }
 416:srcc/gpio.c   **** }
 1628              		.loc 2 416 0
 1629 09b8 00BF     		nop
 1630 09ba 1837     		adds	r7, r7, #24
 1631              		.cfi_def_cfa_offset 8
 1632 09bc BD46     		mov	sp, r7
 1633              		.cfi_def_cfa_register 13
 1634              		@ sp needed
 1635 09be 80BD     		pop	{r7, pc}
 1636              	.L89:
 1637              		.align	2
 1638              	.L88:
 1639 09c0 00000000 		.word	GPIO_ODD_ARR
 1640 09c4 00000000 		.word	GPIO_EVEN_ARR
 1641              		.cfi_endproc
 1642              	.LFE129:
 1644              		.align	1
 1645              		.global	gpio_disable_int
 1646              		.syntax unified
 1647              		.thumb
 1648              		.thumb_func
 1649              		.fpu fpv4-sp-d16
 1651              	gpio_disable_int:
 1652              	.LFB130:
 417:srcc/gpio.c   **** 
 418:srcc/gpio.c   **** //===========================================================================
 419:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_disable_int
 420:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
 421:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º(¶Ë¿ÚºÅ)|(Òý½ÅºÅ)(PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
 422:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£ºµ±Ö¸¶¨¶Ë¿ÚÒý½Å±»¶¨ÒåÎªGPIO¹¦ÄÜÇÒÎªÊäÈëÊ±£¬±¾º¯Êý¹Ø±ÕÒý½ÅÖÐ¶Ï
 423:srcc/gpio.c   **** //×¢          Òâ£º MP432P401RÐ¾Æ¬£¬Ö»ÓÐPORT1~PORT6¿Ú¾ßÓÐGPIOÀàÖÐ¶Ï¹¦ÄÜ
 424:srcc/gpio.c   **** //
 425:srcc/gpio.c   **** //===========================================================================
 426:srcc/gpio.c   **** void gpio_disable_int(uint16_t port_pin)
 427:srcc/gpio.c   **** {
 1653              		.loc 2 427 0
 1654              		.cfi_startproc
 1655              		@ args = 0, pretend = 0, frame = 24
 1656              		@ frame_needed = 1, uses_anonymous_args = 0
 1657 09c8 80B5     		push	{r7, lr}
 1658              		.cfi_def_cfa_offset 8
 1659              		.cfi_offset 7, -8
 1660              		.cfi_offset 14, -4
 1661 09ca 86B0     		sub	sp, sp, #24
 1662              		.cfi_def_cfa_offset 32
 1663 09cc 00AF     		add	r7, sp, #0
 1664              		.cfi_def_cfa_register 7
 1665 09ce 0346     		mov	r3, r0
 1666 09d0 FB80     		strh	r3, [r7, #6]	@ movhi
 428:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
 429:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
 430:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
 431:srcc/gpio.c   **** 	uint8_t port;
 432:srcc/gpio.c   **** 	uint8_t pin;
 433:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 1667              		.loc 2 433 0
 1668 09d2 07F10E02 		add	r2, r7, #14
 1669 09d6 07F10F01 		add	r1, r7, #15
 1670 09da FB88     		ldrh	r3, [r7, #6]
 1671 09dc 1846     		mov	r0, r3
 1672 09de FFF743FB 		bl	gpio_port_pin_resolution
 434:srcc/gpio.c   **** 
 435:srcc/gpio.c   **** 	if(port%2 == 0)
 1673              		.loc 2 435 0
 1674 09e2 FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1675 09e4 03F00103 		and	r3, r3, #1
 1676 09e8 DBB2     		uxtb	r3, r3
 1677 09ea 002B     		cmp	r3, #0
 1678 09ec 18D1     		bne	.L91
 436:srcc/gpio.c   **** 	{
 437:srcc/gpio.c   **** 		gpio_odd_ptr = (DIO_PORT_Odd_Interruptable_Type*) (GPIO_ODD_ARR[port/2]);
 1679              		.loc 2 437 0
 1680 09ee FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1681 09f0 5B08     		lsrs	r3, r3, #1
 1682 09f2 DBB2     		uxtb	r3, r3
 1683 09f4 1A46     		mov	r2, r3
 1684 09f6 2E4B     		ldr	r3, .L102
 1685 09f8 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1686 09fc 3B61     		str	r3, [r7, #16]
 438:srcc/gpio.c   **** 		 BCLR(pin,gpio_odd_ptr->IE);       //½ûÓÃÒý½ÅÖÐ¶Ï
 1687              		.loc 2 438 0
 1688 09fe 3B69     		ldr	r3, [r7, #16]
 1689 0a00 9B7E     		ldrb	r3, [r3, #26]
 1690 0a02 DBB2     		uxtb	r3, r3
 1691 0a04 5AB2     		sxtb	r2, r3
 1692 0a06 BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1693 0a08 1946     		mov	r1, r3
 1694 0a0a 0123     		movs	r3, #1
 1695 0a0c 8B40     		lsls	r3, r3, r1
 1696 0a0e 5BB2     		sxtb	r3, r3
 1697 0a10 DB43     		mvns	r3, r3
 1698 0a12 5BB2     		sxtb	r3, r3
 1699 0a14 1340     		ands	r3, r3, r2
 1700 0a16 5BB2     		sxtb	r3, r3
 1701 0a18 DAB2     		uxtb	r2, r3
 1702 0a1a 3B69     		ldr	r3, [r7, #16]
 1703 0a1c 9A76     		strb	r2, [r3, #26]
 1704 0a1e 19E0     		b	.L92
 1705              	.L91:
 439:srcc/gpio.c   **** 	}
 440:srcc/gpio.c   **** 	else
 441:srcc/gpio.c   **** 	{
 442:srcc/gpio.c   **** 		gpio_even_ptr = (DIO_PORT_Even_Interruptable_Type*) (GPIO_EVEN_ARR[(port-1)/2]);
 1706              		.loc 2 442 0
 1707 0a20 FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1708 0a22 013B     		subs	r3, r3, #1
 1709 0a24 DA0F     		lsrs	r2, r3, #31
 1710 0a26 1344     		add	r3, r3, r2
 1711 0a28 5B10     		asrs	r3, r3, #1
 1712 0a2a 1A46     		mov	r2, r3
 1713 0a2c 214B     		ldr	r3, .L102+4
 1714 0a2e 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1715 0a32 7B61     		str	r3, [r7, #20]
 443:srcc/gpio.c   **** 		 BCLR(pin,gpio_even_ptr->IE);     //½ûÓÃÒý½ÅÖÐ¶Ï
 1716              		.loc 2 443 0
 1717 0a34 7B69     		ldr	r3, [r7, #20]
 1718 0a36 DB7E     		ldrb	r3, [r3, #27]
 1719 0a38 DBB2     		uxtb	r3, r3
 1720 0a3a 5AB2     		sxtb	r2, r3
 1721 0a3c BB7B     		ldrb	r3, [r7, #14]	@ zero_extendqisi2
 1722 0a3e 1946     		mov	r1, r3
 1723 0a40 0123     		movs	r3, #1
 1724 0a42 8B40     		lsls	r3, r3, r1
 1725 0a44 5BB2     		sxtb	r3, r3
 1726 0a46 DB43     		mvns	r3, r3
 1727 0a48 5BB2     		sxtb	r3, r3
 1728 0a4a 1340     		ands	r3, r3, r2
 1729 0a4c 5BB2     		sxtb	r3, r3
 1730 0a4e DAB2     		uxtb	r2, r3
 1731 0a50 7B69     		ldr	r3, [r7, #20]
 1732 0a52 DA76     		strb	r2, [r3, #27]
 1733              	.L92:
 444:srcc/gpio.c   **** 	}
 445:srcc/gpio.c   **** 
 446:srcc/gpio.c   ****     switch(port)
 1734              		.loc 2 446 0
 1735 0a54 FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 1736 0a56 052B     		cmp	r3, #5
 1737 0a58 26D8     		bhi	.L101
 1738 0a5a 01A2     		adr	r2, .L95
 1739 0a5c 52F823F0 		ldr	pc, [r2, r3, lsl #2]
 1740              		.p2align 2
 1741              	.L95:
 1742 0a60 790A0000 		.word	.L94+1
 1743 0a64 810A0000 		.word	.L96+1
 1744 0a68 890A0000 		.word	.L97+1
 1745 0a6c 910A0000 		.word	.L98+1
 1746 0a70 990A0000 		.word	.L99+1
 1747 0a74 A10A0000 		.word	.L100+1
 1748              		.p2align 1
 1749              	.L94:
 447:srcc/gpio.c   ****     {
 448:srcc/gpio.c   ****         case 0://PT1
 449:srcc/gpio.c   ****     	    NVIC_DisableIRQ((IRQn_Type)35);   //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1750              		.loc 2 449 0
 1751 0a78 2320     		movs	r0, #35
 1752 0a7a FFF7DBFA 		bl	NVIC_DisableIRQ
 450:srcc/gpio.c   ****         	break;
 1753              		.loc 2 450 0
 1754 0a7e 13E0     		b	.L93
 1755              	.L96:
 451:srcc/gpio.c   ****         case 1://PT2
 452:srcc/gpio.c   ****         	NVIC_DisableIRQ((IRQn_Type)36);   //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1756              		.loc 2 452 0
 1757 0a80 2420     		movs	r0, #36
 1758 0a82 FFF7D7FA 		bl	NVIC_DisableIRQ
 453:srcc/gpio.c   ****         	break;
 1759              		.loc 2 453 0
 1760 0a86 0FE0     		b	.L93
 1761              	.L97:
 454:srcc/gpio.c   ****         case 2://PT3
 455:srcc/gpio.c   ****         	NVIC_DisableIRQ((IRQn_Type)37);   //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1762              		.loc 2 455 0
 1763 0a88 2520     		movs	r0, #37
 1764 0a8a FFF7D3FA 		bl	NVIC_DisableIRQ
 456:srcc/gpio.c   ****             break;
 1765              		.loc 2 456 0
 1766 0a8e 0BE0     		b	.L93
 1767              	.L98:
 457:srcc/gpio.c   ****         case 3://PT4
 458:srcc/gpio.c   ****         	NVIC_DisableIRQ((IRQn_Type)38);   //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1768              		.loc 2 458 0
 1769 0a90 2620     		movs	r0, #38
 1770 0a92 FFF7CFFA 		bl	NVIC_DisableIRQ
 459:srcc/gpio.c   ****             break;
 1771              		.loc 2 459 0
 1772 0a96 07E0     		b	.L93
 1773              	.L99:
 460:srcc/gpio.c   ****         case 4://PT5
 461:srcc/gpio.c   ****         	NVIC_DisableIRQ((IRQn_Type)39);   //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1774              		.loc 2 461 0
 1775 0a98 2720     		movs	r0, #39
 1776 0a9a FFF7CBFA 		bl	NVIC_DisableIRQ
 462:srcc/gpio.c   ****             break;
 1777              		.loc 2 462 0
 1778 0a9e 03E0     		b	.L93
 1779              	.L100:
 463:srcc/gpio.c   ****         case 5://PT6
 464:srcc/gpio.c   ****         	NVIC_DisableIRQ((IRQn_Type)40);   //¿ªÖÐ¶Ï¿ØÖÆÆ÷IRQÖÐ¶Ï
 1780              		.loc 2 464 0
 1781 0aa0 2820     		movs	r0, #40
 1782 0aa2 FFF7C7FA 		bl	NVIC_DisableIRQ
 465:srcc/gpio.c   ****             break;
 1783              		.loc 2 465 0
 1784 0aa6 00BF     		nop
 1785              	.L93:
 1786              	.L101:
 466:srcc/gpio.c   ****         default:;
 467:srcc/gpio.c   ****      }
 468:srcc/gpio.c   **** }
 1787              		.loc 2 468 0
 1788 0aa8 00BF     		nop
 1789 0aaa 1837     		adds	r7, r7, #24
 1790              		.cfi_def_cfa_offset 8
 1791 0aac BD46     		mov	sp, r7
 1792              		.cfi_def_cfa_register 13
 1793              		@ sp needed
 1794 0aae 80BD     		pop	{r7, pc}
 1795              	.L103:
 1796              		.align	2
 1797              	.L102:
 1798 0ab0 00000000 		.word	GPIO_ODD_ARR
 1799 0ab4 00000000 		.word	GPIO_EVEN_ARR
 1800              		.cfi_endproc
 1801              	.LFE130:
 1803              		.align	1
 1804              		.global	gpio_drive_strength
 1805              		.syntax unified
 1806              		.thumb
 1807              		.thumb_func
 1808              		.fpu fpv4-sp-d16
 1810              	gpio_drive_strength:
 1811              	.LFB131:
 469:srcc/gpio.c   **** 
 470:srcc/gpio.c   **** //===========================================================================
 471:srcc/gpio.c   **** //º¯ÊýÃû³Æ£ºgpio_drive_strength
 472:srcc/gpio.c   **** //º¯Êý·µ»Ø£ºÎÞ
 473:srcc/gpio.c   **** //²ÎÊýËµÃ÷£ºport_pin£º(¶Ë¿ÚºÅ)|(Òý½ÅºÅ)(PORT_2)|(0) ±íÊ¾Îª2¿Ú0ºÅ½Å£©
 474:srcc/gpio.c   **** //       control£º¿ØÖÆÒý½ÅµÄÇý¶¯ÄÜÁ¦£¨Òý½Å±»ÅäÖÃÎªÊý×ÖÊä³öÊ±£¬DSE=1£º¸ßÇý¶¯ÄÜÁ¦£¬DSE=0£ºÕý³£Çý
 475:srcc/gpio.c   **** //                ¶¯ÄÜÁ¦£©
 476:srcc/gpio.c   **** //¹¦ÄÜ¸ÅÒª£º£¨Òý½ÅÇý¶¯ÄÜÁ¦£ºÖ¸Òý½ÅÊäÈë»òÊä³öµçÁ÷µÄ³ÐÊÜÁ¦£¬Ò»°ãÓÃmAµ¥Î»¶ÈÁ¿£¬Õý³£Çý¶¯ÄÜÁ¦5mA,¸ßÇý¶¯Ä
 477:srcc/gpio.c   **** //        Á¦18mA¡££©        µ±Òý½Å±»ÅäÖÃÎªÊý×ÖÊä³öÊ±,¶ÔÒý½ÅµÄÇý¶¯ÄÜÁ¦½øÐÐÉèÖÃ£¬Ö»ÓÐPTB0,PTB1,PTD6,
 478:srcc/gpio.c   **** //        PTD7Í¬Ê±¾ßÓÐ¸ßÇý¶¯ÄÜÁ¦ºÍÕý³£Çý¶¯ÄÜÁ¦,ÕâÐ©Òý½Å¿ÉÓÃÓÚÖ±½ÓÇý¶¯LED»ò¸øMOSFET£¨½ðÑõ°ë³¡Ð§
 479:srcc/gpio.c   **** //        ¾§Ìå¹Ü£©¹©µç£¬¸Ãº¯ÊýÖ»ÊÊÓÃÓÚÉÏÊö4¸öÒý½Å¡£
 480:srcc/gpio.c   **** //===========================================================================
 481:srcc/gpio.c   **** void gpio_drive_strength(uint16_t port_pin, uint8_t control)
 482:srcc/gpio.c   **** {
 1812              		.loc 2 482 0
 1813              		.cfi_startproc
 1814              		@ args = 0, pretend = 0, frame = 24
 1815              		@ frame_needed = 1, uses_anonymous_args = 0
 1816 0ab8 80B5     		push	{r7, lr}
 1817              		.cfi_def_cfa_offset 8
 1818              		.cfi_offset 7, -8
 1819              		.cfi_offset 14, -4
 1820 0aba 86B0     		sub	sp, sp, #24
 1821              		.cfi_def_cfa_offset 32
 1822 0abc 00AF     		add	r7, sp, #0
 1823              		.cfi_def_cfa_register 7
 1824 0abe 0346     		mov	r3, r0
 1825 0ac0 0A46     		mov	r2, r1
 1826 0ac2 FB80     		strh	r3, [r7, #6]	@ movhi
 1827 0ac4 1346     		mov	r3, r2
 1828 0ac6 7B71     		strb	r3, [r7, #5]
 483:srcc/gpio.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
 484:srcc/gpio.c   **** 	DIO_PORT_Odd_Interruptable_Type* gpio_odd_ptr;
 485:srcc/gpio.c   **** 	DIO_PORT_Even_Interruptable_Type* gpio_even_ptr;
 486:srcc/gpio.c   **** 	DIO_PORT_Not_Interruptable_Type* gpio_not_ptr;
 487:srcc/gpio.c   **** 	uint8_t port;
 488:srcc/gpio.c   **** 	uint8_t pin;
 489:srcc/gpio.c   **** 	gpio_port_pin_resolution(port_pin , &port , &pin);
 1829              		.loc 2 489 0
 1830 0ac8 07F10A02 		add	r2, r7, #10
 1831 0acc 07F10B01 		add	r1, r7, #11
 1832 0ad0 FB88     		ldrh	r3, [r7, #6]
 1833 0ad2 1846     		mov	r0, r3
 1834 0ad4 FFF7C8FA 		bl	gpio_port_pin_resolution
 490:srcc/gpio.c   **** 
 491:srcc/gpio.c   **** 	//¸ù¾Ý´øÈë²ÎÊýport£¬¸ø¾Ö²¿±äÁ¿port_ptr¸³Öµ
 492:srcc/gpio.c   **** 	if(port >= 10)
 1835              		.loc 2 492 0
 1836 0ad8 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1837 0ada 092B     		cmp	r3, #9
 1838 0adc 34D9     		bls	.L105
 493:srcc/gpio.c   **** 	{
 494:srcc/gpio.c   **** 		gpio_not_ptr = (DIO_PORT_Not_Interruptable_Type*)PJ;
 1839              		.loc 2 494 0
 1840 0ade 5B4B     		ldr	r3, .L114
 1841 0ae0 FB60     		str	r3, [r7, #12]
 495:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýcontrol£¬¾ö¶¨Òý½ÅÎªÊä³ö¸ßµçÁ÷»¹ÊÇÕý³£µçÁ÷
 496:srcc/gpio.c   **** 		BCLR(pin,gpio_not_ptr->DS);
 1842              		.loc 2 496 0
 1843 0ae2 FB68     		ldr	r3, [r7, #12]
 1844 0ae4 1B89     		ldrh	r3, [r3, #8]	@ movhi
 1845 0ae6 9BB2     		uxth	r3, r3
 1846 0ae8 1AB2     		sxth	r2, r3
 1847 0aea BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1848 0aec 1946     		mov	r1, r3
 1849 0aee 0123     		movs	r3, #1
 1850 0af0 8B40     		lsls	r3, r3, r1
 1851 0af2 1BB2     		sxth	r3, r3
 1852 0af4 DB43     		mvns	r3, r3
 1853 0af6 1BB2     		sxth	r3, r3
 1854 0af8 1340     		ands	r3, r3, r2
 1855 0afa 1BB2     		sxth	r3, r3
 1856 0afc 9AB2     		uxth	r2, r3
 1857 0afe FB68     		ldr	r3, [r7, #12]
 1858 0b00 1A81     		strh	r2, [r3, #8]	@ movhi
 497:srcc/gpio.c   **** 		if (1 == control)
 1859              		.loc 2 497 0
 1860 0b02 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 1861 0b04 012B     		cmp	r3, #1
 1862 0b06 0ED1     		bne	.L106
 498:srcc/gpio.c   **** 		    BSET(pin,gpio_not_ptr->DS);
 1863              		.loc 2 498 0
 1864 0b08 FB68     		ldr	r3, [r7, #12]
 1865 0b0a 1B89     		ldrh	r3, [r3, #8]	@ movhi
 1866 0b0c 9BB2     		uxth	r3, r3
 1867 0b0e 1AB2     		sxth	r2, r3
 1868 0b10 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1869 0b12 1946     		mov	r1, r3
 1870 0b14 0123     		movs	r3, #1
 1871 0b16 8B40     		lsls	r3, r3, r1
 1872 0b18 1BB2     		sxth	r3, r3
 1873 0b1a 1343     		orrs	r3, r3, r2
 1874 0b1c 1BB2     		sxth	r3, r3
 1875 0b1e 9AB2     		uxth	r2, r3
 1876 0b20 FB68     		ldr	r3, [r7, #12]
 1877 0b22 1A81     		strh	r2, [r3, #8]	@ movhi
 499:srcc/gpio.c   **** 		else
 500:srcc/gpio.c   **** 			BCLR(pin,gpio_not_ptr->DS);
 501:srcc/gpio.c   **** 	}
 502:srcc/gpio.c   **** 	else if(port%2 == 0)
 503:srcc/gpio.c   **** 	{
 504:srcc/gpio.c   **** 		gpio_odd_ptr = (DIO_PORT_Odd_Interruptable_Type*) (GPIO_ODD_ARR[port/2]);
 505:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýcontrol£¬¾ö¶¨Òý½ÅÎªÊä³ö¸ßµçÁ÷»¹ÊÇÕý³£µçÁ÷
 506:srcc/gpio.c   **** 		BCLR(pin,gpio_odd_ptr->DS);
 507:srcc/gpio.c   **** 		if (1 == control)
 508:srcc/gpio.c   **** 		    BSET(pin,gpio_odd_ptr->DS);
 509:srcc/gpio.c   **** 		else
 510:srcc/gpio.c   **** 			BCLR(pin,gpio_odd_ptr->DS);
 511:srcc/gpio.c   **** 	}
 512:srcc/gpio.c   **** 	else
 513:srcc/gpio.c   **** 	{
 514:srcc/gpio.c   **** 		gpio_even_ptr = (DIO_PORT_Even_Interruptable_Type*) (GPIO_EVEN_ARR[(port-1)/2]);
 515:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýcontrol£¬¾ö¶¨Òý½ÅÎªÊä³ö¸ßµçÁ÷»¹ÊÇÕý³£µçÁ÷
 516:srcc/gpio.c   **** 		BCLR(pin,gpio_even_ptr->DS);
 517:srcc/gpio.c   **** 		if (1 == control)
 518:srcc/gpio.c   **** 		    BSET(pin,gpio_even_ptr->DS);
 519:srcc/gpio.c   **** 		else
 520:srcc/gpio.c   **** 			BCLR(pin,gpio_even_ptr->DS);
 521:srcc/gpio.c   **** 	}
 522:srcc/gpio.c   **** }
 1878              		.loc 2 522 0
 1879 0b24 8DE0     		b	.L113
 1880              	.L106:
 500:srcc/gpio.c   **** 	}
 1881              		.loc 2 500 0
 1882 0b26 FB68     		ldr	r3, [r7, #12]
 1883 0b28 1B89     		ldrh	r3, [r3, #8]	@ movhi
 1884 0b2a 9BB2     		uxth	r3, r3
 1885 0b2c 1AB2     		sxth	r2, r3
 1886 0b2e BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1887 0b30 1946     		mov	r1, r3
 1888 0b32 0123     		movs	r3, #1
 1889 0b34 8B40     		lsls	r3, r3, r1
 1890 0b36 1BB2     		sxth	r3, r3
 1891 0b38 DB43     		mvns	r3, r3
 1892 0b3a 1BB2     		sxth	r3, r3
 1893 0b3c 1340     		ands	r3, r3, r2
 1894 0b3e 1BB2     		sxth	r3, r3
 1895 0b40 9AB2     		uxth	r2, r3
 1896 0b42 FB68     		ldr	r3, [r7, #12]
 1897 0b44 1A81     		strh	r2, [r3, #8]	@ movhi
 1898              		.loc 2 522 0
 1899 0b46 7CE0     		b	.L113
 1900              	.L105:
 502:srcc/gpio.c   **** 	{
 1901              		.loc 2 502 0
 1902 0b48 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1903 0b4a 03F00103 		and	r3, r3, #1
 1904 0b4e DBB2     		uxtb	r3, r3
 1905 0b50 002B     		cmp	r3, #0
 1906 0b52 3AD1     		bne	.L109
 504:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýcontrol£¬¾ö¶¨Òý½ÅÎªÊä³ö¸ßµçÁ÷»¹ÊÇÕý³£µçÁ÷
 1907              		.loc 2 504 0
 1908 0b54 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1909 0b56 5B08     		lsrs	r3, r3, #1
 1910 0b58 DBB2     		uxtb	r3, r3
 1911 0b5a 1A46     		mov	r2, r3
 1912 0b5c 3C4B     		ldr	r3, .L114+4
 1913 0b5e 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1914 0b62 3B61     		str	r3, [r7, #16]
 506:srcc/gpio.c   **** 		if (1 == control)
 1915              		.loc 2 506 0
 1916 0b64 3B69     		ldr	r3, [r7, #16]
 1917 0b66 1B7A     		ldrb	r3, [r3, #8]
 1918 0b68 DBB2     		uxtb	r3, r3
 1919 0b6a 5AB2     		sxtb	r2, r3
 1920 0b6c BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1921 0b6e 1946     		mov	r1, r3
 1922 0b70 0123     		movs	r3, #1
 1923 0b72 8B40     		lsls	r3, r3, r1
 1924 0b74 5BB2     		sxtb	r3, r3
 1925 0b76 DB43     		mvns	r3, r3
 1926 0b78 5BB2     		sxtb	r3, r3
 1927 0b7a 1340     		ands	r3, r3, r2
 1928 0b7c 5BB2     		sxtb	r3, r3
 1929 0b7e DAB2     		uxtb	r2, r3
 1930 0b80 3B69     		ldr	r3, [r7, #16]
 1931 0b82 1A72     		strb	r2, [r3, #8]
 507:srcc/gpio.c   **** 		    BSET(pin,gpio_odd_ptr->DS);
 1932              		.loc 2 507 0
 1933 0b84 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 1934 0b86 012B     		cmp	r3, #1
 1935 0b88 0ED1     		bne	.L110
 508:srcc/gpio.c   **** 		else
 1936              		.loc 2 508 0
 1937 0b8a 3B69     		ldr	r3, [r7, #16]
 1938 0b8c 1B7A     		ldrb	r3, [r3, #8]
 1939 0b8e DBB2     		uxtb	r3, r3
 1940 0b90 5AB2     		sxtb	r2, r3
 1941 0b92 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1942 0b94 1946     		mov	r1, r3
 1943 0b96 0123     		movs	r3, #1
 1944 0b98 8B40     		lsls	r3, r3, r1
 1945 0b9a 5BB2     		sxtb	r3, r3
 1946 0b9c 1343     		orrs	r3, r3, r2
 1947 0b9e 5BB2     		sxtb	r3, r3
 1948 0ba0 DAB2     		uxtb	r2, r3
 1949 0ba2 3B69     		ldr	r3, [r7, #16]
 1950 0ba4 1A72     		strb	r2, [r3, #8]
 1951              		.loc 2 522 0
 1952 0ba6 4CE0     		b	.L113
 1953              	.L110:
 510:srcc/gpio.c   **** 	}
 1954              		.loc 2 510 0
 1955 0ba8 3B69     		ldr	r3, [r7, #16]
 1956 0baa 1B7A     		ldrb	r3, [r3, #8]
 1957 0bac DBB2     		uxtb	r3, r3
 1958 0bae 5AB2     		sxtb	r2, r3
 1959 0bb0 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1960 0bb2 1946     		mov	r1, r3
 1961 0bb4 0123     		movs	r3, #1
 1962 0bb6 8B40     		lsls	r3, r3, r1
 1963 0bb8 5BB2     		sxtb	r3, r3
 1964 0bba DB43     		mvns	r3, r3
 1965 0bbc 5BB2     		sxtb	r3, r3
 1966 0bbe 1340     		ands	r3, r3, r2
 1967 0bc0 5BB2     		sxtb	r3, r3
 1968 0bc2 DAB2     		uxtb	r2, r3
 1969 0bc4 3B69     		ldr	r3, [r7, #16]
 1970 0bc6 1A72     		strb	r2, [r3, #8]
 1971              		.loc 2 522 0
 1972 0bc8 3BE0     		b	.L113
 1973              	.L109:
 514:srcc/gpio.c   **** 	    //¸ù¾Ý´øÈë²ÎÊýcontrol£¬¾ö¶¨Òý½ÅÎªÊä³ö¸ßµçÁ÷»¹ÊÇÕý³£µçÁ÷
 1974              		.loc 2 514 0
 1975 0bca FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 1976 0bcc 013B     		subs	r3, r3, #1
 1977 0bce DA0F     		lsrs	r2, r3, #31
 1978 0bd0 1344     		add	r3, r3, r2
 1979 0bd2 5B10     		asrs	r3, r3, #1
 1980 0bd4 1A46     		mov	r2, r3
 1981 0bd6 1F4B     		ldr	r3, .L114+8
 1982 0bd8 53F82230 		ldr	r3, [r3, r2, lsl #2]
 1983 0bdc 7B61     		str	r3, [r7, #20]
 516:srcc/gpio.c   **** 		if (1 == control)
 1984              		.loc 2 516 0
 1985 0bde 7B69     		ldr	r3, [r7, #20]
 1986 0be0 5B7A     		ldrb	r3, [r3, #9]
 1987 0be2 DBB2     		uxtb	r3, r3
 1988 0be4 5AB2     		sxtb	r2, r3
 1989 0be6 BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 1990 0be8 1946     		mov	r1, r3
 1991 0bea 0123     		movs	r3, #1
 1992 0bec 8B40     		lsls	r3, r3, r1
 1993 0bee 5BB2     		sxtb	r3, r3
 1994 0bf0 DB43     		mvns	r3, r3
 1995 0bf2 5BB2     		sxtb	r3, r3
 1996 0bf4 1340     		ands	r3, r3, r2
 1997 0bf6 5BB2     		sxtb	r3, r3
 1998 0bf8 DAB2     		uxtb	r2, r3
 1999 0bfa 7B69     		ldr	r3, [r7, #20]
 2000 0bfc 5A72     		strb	r2, [r3, #9]
 517:srcc/gpio.c   **** 		    BSET(pin,gpio_even_ptr->DS);
 2001              		.loc 2 517 0
 2002 0bfe 7B79     		ldrb	r3, [r7, #5]	@ zero_extendqisi2
 2003 0c00 012B     		cmp	r3, #1
 2004 0c02 0ED1     		bne	.L112
 518:srcc/gpio.c   **** 		else
 2005              		.loc 2 518 0
 2006 0c04 7B69     		ldr	r3, [r7, #20]
 2007 0c06 5B7A     		ldrb	r3, [r3, #9]
 2008 0c08 DBB2     		uxtb	r3, r3
 2009 0c0a 5AB2     		sxtb	r2, r3
 2010 0c0c BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 2011 0c0e 1946     		mov	r1, r3
 2012 0c10 0123     		movs	r3, #1
 2013 0c12 8B40     		lsls	r3, r3, r1
 2014 0c14 5BB2     		sxtb	r3, r3
 2015 0c16 1343     		orrs	r3, r3, r2
 2016 0c18 5BB2     		sxtb	r3, r3
 2017 0c1a DAB2     		uxtb	r2, r3
 2018 0c1c 7B69     		ldr	r3, [r7, #20]
 2019 0c1e 5A72     		strb	r2, [r3, #9]
 2020              		.loc 2 522 0
 2021 0c20 0FE0     		b	.L113
 2022              	.L112:
 520:srcc/gpio.c   **** 	}
 2023              		.loc 2 520 0
 2024 0c22 7B69     		ldr	r3, [r7, #20]
 2025 0c24 5B7A     		ldrb	r3, [r3, #9]
 2026 0c26 DBB2     		uxtb	r3, r3
 2027 0c28 5AB2     		sxtb	r2, r3
 2028 0c2a BB7A     		ldrb	r3, [r7, #10]	@ zero_extendqisi2
 2029 0c2c 1946     		mov	r1, r3
 2030 0c2e 0123     		movs	r3, #1
 2031 0c30 8B40     		lsls	r3, r3, r1
 2032 0c32 5BB2     		sxtb	r3, r3
 2033 0c34 DB43     		mvns	r3, r3
 2034 0c36 5BB2     		sxtb	r3, r3
 2035 0c38 1340     		ands	r3, r3, r2
 2036 0c3a 5BB2     		sxtb	r3, r3
 2037 0c3c DAB2     		uxtb	r2, r3
 2038 0c3e 7B69     		ldr	r3, [r7, #20]
 2039 0c40 5A72     		strb	r2, [r3, #9]
 2040              	.L113:
 2041              		.loc 2 522 0
 2042 0c42 00BF     		nop
 2043 0c44 1837     		adds	r7, r7, #24
 2044              		.cfi_def_cfa_offset 8
 2045 0c46 BD46     		mov	sp, r7
 2046              		.cfi_def_cfa_register 13
 2047              		@ sp needed
 2048 0c48 80BD     		pop	{r7, pc}
 2049              	.L115:
 2050 0c4a 00BF     		.align	2
 2051              	.L114:
 2052 0c4c 204D0040 		.word	1073761568
 2053 0c50 00000000 		.word	GPIO_ODD_ARR
 2054 0c54 00000000 		.word	GPIO_EVEN_ARR
 2055              		.cfi_endproc
 2056              	.LFE131:
 2058              	.Letext0:
 2059              		.file 3 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 2060              		.file 4 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 2061              		.file 5 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH04-GPIO\\
 2062              		.file 6 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH04-GPIO\\
 2063              		.file 7 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\lock.h"
 2064              		.file 8 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\_types.h"
 2065              		.file 9 "d:\\ahl-gec-ide(4.20)\\gcc\\lib\\gcc\\arm-none-eabi\\7.2.1\\include\\stddef.h"
 2066              		.file 10 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\reent.h"
DEFINED SYMBOLS
                            *ABS*:00000000 gpio.c
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:17     .text:00000000 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:23     .text:00000000 NVIC_EnableIRQ
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:63     .text:00000030 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:67     .text:00000034 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:73     .text:00000034 NVIC_DisableIRQ
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:113    .text:00000064 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:122    .data:00000000 GPIO_ODD_ARR
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:119    .data:00000000 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:132    .data:00000014 GPIO_EVEN_ARR
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:139    .text:00000068 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:145    .text:00000068 gpio_port_pin_resolution
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:197    .text:00000096 gpio_init
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:584    .text:00000334 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:589    .text:00000340 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:624    .text:00000368 gpio_set
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:815    .text:0000049c $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:821    .text:000004a8 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:828    .text:000004a8 gpio_get
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:945    .text:0000055c $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:951    .text:00000568 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:958    .text:00000568 gpio_reverse
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1164   .text:000006c4 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1170   .text:000006d0 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1177   .text:000006d0 gpio_pull
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1368   .text:00000804 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1374   .text:00000810 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1381   .text:00000810 gpio_enable_int
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1583   .text:00000970 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1589   .text:00000988 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1639   .text:000009c0 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1644   .text:000009c8 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1651   .text:000009c8 gpio_disable_int
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1742   .text:00000a60 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1748   .text:00000a78 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1798   .text:00000ab0 $d
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1803   .text:00000ab8 $t
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:1810   .text:00000ab8 gpio_drive_strength
C:\Users\lenovo\AppData\Local\Temp\ccu4aY8z.s:2052   .text:00000c4c $d

NO UNDEFINED SYMBOLS
