   1              		.cpu cortex-m4
   2              		.eabi_attribute 27, 1
   3              		.eabi_attribute 28, 1
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 6
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"system_msp432p401r.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.global	SystemCoreClock
  18              		.data
  19              		.align	2
  22              	SystemCoreClock:
  23 0000 006CDC02 		.word	48000000
  24              		.text
  25              		.align	1
  26              		.global	SystemCoreClockUpdate
  27              		.syntax unified
  28              		.thumb
  29              		.thumb_func
  30              		.fpu fpv4-sp-d16
  32              	SystemCoreClockUpdate:
  33              	.LFB123:
  34              		.file 1 "srcc/system_msp432p401r.c"
   1:srcc/system_msp432p401r.c **** /******************************************************************************
   2:srcc/system_msp432p401r.c **** * @file     system_msp432p401r.c
   3:srcc/system_msp432p401r.c **** * @brief    CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
   4:srcc/system_msp432p401r.c **** *           MSP432P401R
   5:srcc/system_msp432p401r.c **** * @version  V2.201
   6:srcc/system_msp432p401r.c **** * @date     2016-06-02
   7:srcc/system_msp432p401r.c **** *
   8:srcc/system_msp432p401r.c **** * @note     View configuration instructions embedded in comments
   9:srcc/system_msp432p401r.c **** *
  10:srcc/system_msp432p401r.c **** ******************************************************************************/
  11:srcc/system_msp432p401r.c **** //*****************************************************************************
  12:srcc/system_msp432p401r.c **** //
  13:srcc/system_msp432p401r.c **** // Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
  14:srcc/system_msp432p401r.c **** //
  15:srcc/system_msp432p401r.c **** // Redistribution and use in source and binary forms, with or without
  16:srcc/system_msp432p401r.c **** // modification, are permitted provided that the following conditions
  17:srcc/system_msp432p401r.c **** // are met:
  18:srcc/system_msp432p401r.c **** //
  19:srcc/system_msp432p401r.c **** //  Redistributions of source code must retain the above copyright
  20:srcc/system_msp432p401r.c **** //  notice, this list of conditions and the following disclaimer.
  21:srcc/system_msp432p401r.c **** //
  22:srcc/system_msp432p401r.c **** //  Redistributions in binary form must reproduce the above copyright
  23:srcc/system_msp432p401r.c **** //  notice, this list of conditions and the following disclaimer in the
  24:srcc/system_msp432p401r.c **** //  documentation and/or other materials provided with the
  25:srcc/system_msp432p401r.c **** //  distribution.
  26:srcc/system_msp432p401r.c **** //
  27:srcc/system_msp432p401r.c **** //  Neither the name of Texas Instruments Incorporated nor the names of
  28:srcc/system_msp432p401r.c **** //  its contributors may be used to endorse or promote products derived
  29:srcc/system_msp432p401r.c **** //  from this software without specific prior written permission.
  30:srcc/system_msp432p401r.c **** //
  31:srcc/system_msp432p401r.c **** // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32:srcc/system_msp432p401r.c **** // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33:srcc/system_msp432p401r.c **** // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  34:srcc/system_msp432p401r.c **** // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35:srcc/system_msp432p401r.c **** // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  36:srcc/system_msp432p401r.c **** // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  37:srcc/system_msp432p401r.c **** // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38:srcc/system_msp432p401r.c **** // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  39:srcc/system_msp432p401r.c **** // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40:srcc/system_msp432p401r.c **** // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41:srcc/system_msp432p401r.c **** // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42:srcc/system_msp432p401r.c **** //
  43:srcc/system_msp432p401r.c **** //*****************************************************************************
  44:srcc/system_msp432p401r.c **** 
  45:srcc/system_msp432p401r.c **** #include <stdint.h>
  46:srcc/system_msp432p401r.c **** #include "msp432.h"
  47:srcc/system_msp432p401r.c **** 
  48:srcc/system_msp432p401r.c **** /*--------------------- Configuration Instructions ----------------------------
  49:srcc/system_msp432p401r.c ****    1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
  50:srcc/system_msp432p401r.c ****    #define __HALT_WDT       1
  51:srcc/system_msp432p401r.c ****    2. Insert your desired CPU frequency in Hz at:
  52:srcc/system_msp432p401r.c ****    #define __SYSTEM_CLOCK   12000000
  53:srcc/system_msp432p401r.c ****    3. If you prefer the DC-DC power regulator (more efficient at higher
  54:srcc/system_msp432p401r.c ****        frequencies), set the __REGULATOR to 1:
  55:srcc/system_msp432p401r.c ****    #define __REGULATOR      1
  56:srcc/system_msp432p401r.c ****  *---------------------------------------------------------------------------*/
  57:srcc/system_msp432p401r.c **** 
  58:srcc/system_msp432p401r.c **** /*--------------------- Watchdog Timer Configuration ------------------------*/
  59:srcc/system_msp432p401r.c **** //  Halt the Watchdog Timer
  60:srcc/system_msp432p401r.c **** //     <0> Do not halt the WDT
  61:srcc/system_msp432p401r.c **** //     <1> Halt the WDT
  62:srcc/system_msp432p401r.c **** #define __HALT_WDT         1
  63:srcc/system_msp432p401r.c **** 
  64:srcc/system_msp432p401r.c **** /*--------------------- CPU Frequency Configuration -------------------------*/
  65:srcc/system_msp432p401r.c **** //  CPU Frequency
  66:srcc/system_msp432p401r.c **** //     <1500000> 1.5 MHz
  67:srcc/system_msp432p401r.c **** //     <3000000> 3 MHz
  68:srcc/system_msp432p401r.c **** //     <12000000> 12 MHz
  69:srcc/system_msp432p401r.c **** //     <24000000> 24 MHz
  70:srcc/system_msp432p401r.c **** //     <48000000> 48 MHz
  71:srcc/system_msp432p401r.c **** #define  __SYSTEM_CLOCK    48000000
  72:srcc/system_msp432p401r.c **** 
  73:srcc/system_msp432p401r.c **** /*--------------------- Power Regulator Configuration -----------------------*/
  74:srcc/system_msp432p401r.c **** //  Power Regulator Mode
  75:srcc/system_msp432p401r.c **** //     <0> LDO
  76:srcc/system_msp432p401r.c **** //     <1> DC-DC
  77:srcc/system_msp432p401r.c **** #define __REGULATOR        0
  78:srcc/system_msp432p401r.c **** 
  79:srcc/system_msp432p401r.c **** /*----------------------------------------------------------------------------
  80:srcc/system_msp432p401r.c ****    Define clocks, used for SystemCoreClockUpdate()
  81:srcc/system_msp432p401r.c ****  *---------------------------------------------------------------------------*/
  82:srcc/system_msp432p401r.c **** #define __VLOCLK           10000
  83:srcc/system_msp432p401r.c **** #define __MODCLK           24000000
  84:srcc/system_msp432p401r.c **** #define __LFXT             32768
  85:srcc/system_msp432p401r.c **** #define __HFXT             48000000
  86:srcc/system_msp432p401r.c **** 
  87:srcc/system_msp432p401r.c **** /*----------------------------------------------------------------------------
  88:srcc/system_msp432p401r.c ****    Clock Variable definitions
  89:srcc/system_msp432p401r.c ****  *---------------------------------------------------------------------------*/
  90:srcc/system_msp432p401r.c **** uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
  91:srcc/system_msp432p401r.c **** 
  92:srcc/system_msp432p401r.c **** /**
  93:srcc/system_msp432p401r.c ****  * Update SystemCoreClock variable
  94:srcc/system_msp432p401r.c ****  *
  95:srcc/system_msp432p401r.c ****  * @param  none
  96:srcc/system_msp432p401r.c ****  * @return none
  97:srcc/system_msp432p401r.c ****  *
  98:srcc/system_msp432p401r.c ****  * @brief  Updates the SystemCoreClock with current core Clock
  99:srcc/system_msp432p401r.c ****  *         retrieved from cpu registers.
 100:srcc/system_msp432p401r.c ****  */
 101:srcc/system_msp432p401r.c **** void SystemCoreClockUpdate(void)
 102:srcc/system_msp432p401r.c **** {
  35              		.loc 1 102 0
  36              		.cfi_startproc
  37              		@ args = 0, pretend = 0, frame = 32
  38              		@ frame_needed = 1, uses_anonymous_args = 0
  39              		@ link register save eliminated.
  40 0000 80B4     		push	{r7}
  41              		.cfi_def_cfa_offset 4
  42              		.cfi_offset 7, -4
  43 0002 89B0     		sub	sp, sp, #36
  44              		.cfi_def_cfa_offset 40
  45 0004 00AF     		add	r7, sp, #0
  46              		.cfi_def_cfa_register 7
 103:srcc/system_msp432p401r.c ****     uint32_t source, divider;
 104:srcc/system_msp432p401r.c ****     uint8_t dividerValue;
 105:srcc/system_msp432p401r.c **** 
 106:srcc/system_msp432p401r.c ****     float dcoConst;
 107:srcc/system_msp432p401r.c ****     int32_t calVal;
 108:srcc/system_msp432p401r.c ****     uint32_t centeredFreq;
 109:srcc/system_msp432p401r.c ****     int16_t dcoTune;
 110:srcc/system_msp432p401r.c **** 
 111:srcc/system_msp432p401r.c ****     divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
  47              		.loc 1 111 0
  48 0006 A64B     		ldr	r3, .L40
  49 0008 9B68     		ldr	r3, [r3, #8]
  50 000a 1B0C     		lsrs	r3, r3, #16
  51 000c 03F00703 		and	r3, r3, #7
  52 0010 FB60     		str	r3, [r7, #12]
 112:srcc/system_msp432p401r.c ****     dividerValue = 1 << divider;
  53              		.loc 1 112 0
  54 0012 0122     		movs	r2, #1
  55 0014 FB68     		ldr	r3, [r7, #12]
  56 0016 02FA03F3 		lsl	r3, r2, r3
  57 001a FB72     		strb	r3, [r7, #11]
 113:srcc/system_msp432p401r.c ****     source = CS->CTL1 & CS_CTL1_SELM_MASK;
  58              		.loc 1 113 0
  59 001c A04B     		ldr	r3, .L40
  60 001e 9B68     		ldr	r3, [r3, #8]
  61 0020 03F00703 		and	r3, r3, #7
  62 0024 7B60     		str	r3, [r7, #4]
 114:srcc/system_msp432p401r.c **** 
 115:srcc/system_msp432p401r.c ****     switch(source)
  63              		.loc 1 115 0
  64 0026 7B68     		ldr	r3, [r7, #4]
  65 0028 052B     		cmp	r3, #5
  66 002a 00F25F81 		bhi	.L38
  67 002e 01A2     		adr	r2, .L4
  68 0030 52F823F0 		ldr	pc, [r2, r3, lsl #2]
  69              		.p2align 2
  70              	.L4:
  71 0034 4D000000 		.word	.L3+1
  72 0038 CD000000 		.word	.L5+1
  73 003c DF000000 		.word	.L6+1
  74 0040 0D010000 		.word	.L7+1
  75 0044 23020000 		.word	.L8+1
  76 0048 33020000 		.word	.L9+1
  77              		.p2align 1
  78              	.L3:
 116:srcc/system_msp432p401r.c ****     {
 117:srcc/system_msp432p401r.c ****     case CS_CTL1_SELM__LFXTCLK:
 118:srcc/system_msp432p401r.c ****         if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
  79              		.loc 1 118 0
  80 004c 954B     		ldr	r3, .L40+4
  81 004e 1B78     		ldrb	r3, [r3]
  82 0050 DBB2     		uxtb	r3, r3
  83 0052 002B     		cmp	r3, #0
  84 0054 31D0     		beq	.L10
 119:srcc/system_msp432p401r.c ****         {
 120:srcc/system_msp432p401r.c ****             // Clear interrupt flag
 121:srcc/system_msp432p401r.c ****             CS->KEY = CS_KEY_VAL;
  85              		.loc 1 121 0
  86 0056 924B     		ldr	r3, .L40
  87 0058 46F65A12 		movw	r2, #26970
  88 005c 1A60     		str	r2, [r3]
 122:srcc/system_msp432p401r.c ****             CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
  89              		.loc 1 122 0
  90 005e 904B     		ldr	r3, .L40
  91 0060 1B6D     		ldr	r3, [r3, #80]
  92 0062 8F4A     		ldr	r2, .L40
  93 0064 43F00103 		orr	r3, r3, #1
  94 0068 1365     		str	r3, [r2, #80]
 123:srcc/system_msp432p401r.c ****             CS->KEY = 1;
  95              		.loc 1 123 0
  96 006a 8D4B     		ldr	r3, .L40
  97 006c 0122     		movs	r2, #1
  98 006e 1A60     		str	r2, [r3]
 124:srcc/system_msp432p401r.c **** 
 125:srcc/system_msp432p401r.c ****             if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
  99              		.loc 1 125 0
 100 0070 8C4B     		ldr	r3, .L40+4
 101 0072 1B78     		ldrb	r3, [r3]
 102 0074 DBB2     		uxtb	r3, r3
 103 0076 002B     		cmp	r3, #0
 104 0078 16D0     		beq	.L11
 126:srcc/system_msp432p401r.c ****             {
 127:srcc/system_msp432p401r.c ****                 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
 105              		.loc 1 127 0
 106 007a 8B4B     		ldr	r3, .L40+8
 107 007c 1B78     		ldrb	r3, [r3]
 108 007e DBB2     		uxtb	r3, r3
 109 0080 002B     		cmp	r3, #0
 110 0082 08D0     		beq	.L12
 128:srcc/system_msp432p401r.c ****                 {
 129:srcc/system_msp432p401r.c ****                     SystemCoreClock = (128000 / dividerValue);
 111              		.loc 1 129 0
 112 0084 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 113 0086 4FF4FA32 		mov	r2, #128000
 114 008a 92FBF3F3 		sdiv	r3, r2, r3
 115 008e 1A46     		mov	r2, r3
 116 0090 864B     		ldr	r3, .L40+12
 117 0092 1A60     		str	r2, [r3]
 130:srcc/system_msp432p401r.c ****                 }
 131:srcc/system_msp432p401r.c ****                 else
 132:srcc/system_msp432p401r.c ****                 {
 133:srcc/system_msp432p401r.c ****                     SystemCoreClock = (32000 / dividerValue);
 134:srcc/system_msp432p401r.c ****                 }
 135:srcc/system_msp432p401r.c ****             }
 136:srcc/system_msp432p401r.c ****             else
 137:srcc/system_msp432p401r.c ****             {
 138:srcc/system_msp432p401r.c ****                 SystemCoreClock = __LFXT / dividerValue;
 139:srcc/system_msp432p401r.c ****             }
 140:srcc/system_msp432p401r.c ****         }
 141:srcc/system_msp432p401r.c ****         else
 142:srcc/system_msp432p401r.c ****         {
 143:srcc/system_msp432p401r.c ****             SystemCoreClock = __LFXT / dividerValue;
 144:srcc/system_msp432p401r.c ****         }
 145:srcc/system_msp432p401r.c ****         break;
 118              		.loc 1 145 0
 119 0094 2AE1     		b	.L2
 120              	.L12:
 133:srcc/system_msp432p401r.c ****                 }
 121              		.loc 1 133 0
 122 0096 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 123 0098 4FF4FA42 		mov	r2, #32000
 124 009c 92FBF3F3 		sdiv	r3, r2, r3
 125 00a0 1A46     		mov	r2, r3
 126 00a2 824B     		ldr	r3, .L40+12
 127 00a4 1A60     		str	r2, [r3]
 128              		.loc 1 145 0
 129 00a6 21E1     		b	.L2
 130              	.L11:
 138:srcc/system_msp432p401r.c ****             }
 131              		.loc 1 138 0
 132 00a8 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 133 00aa 4FF40042 		mov	r2, #32768
 134 00ae 92FBF3F3 		sdiv	r3, r2, r3
 135 00b2 1A46     		mov	r2, r3
 136 00b4 7D4B     		ldr	r3, .L40+12
 137 00b6 1A60     		str	r2, [r3]
 138              		.loc 1 145 0
 139 00b8 18E1     		b	.L2
 140              	.L10:
 143:srcc/system_msp432p401r.c ****         }
 141              		.loc 1 143 0
 142 00ba FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 143 00bc 4FF40042 		mov	r2, #32768
 144 00c0 92FBF3F3 		sdiv	r3, r2, r3
 145 00c4 1A46     		mov	r2, r3
 146 00c6 794B     		ldr	r3, .L40+12
 147 00c8 1A60     		str	r2, [r3]
 148              		.loc 1 145 0
 149 00ca 0FE1     		b	.L2
 150              	.L5:
 146:srcc/system_msp432p401r.c ****     case CS_CTL1_SELM__VLOCLK:
 147:srcc/system_msp432p401r.c ****         SystemCoreClock = __VLOCLK / dividerValue;
 151              		.loc 1 147 0
 152 00cc FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 153 00ce 42F21072 		movw	r2, #10000
 154 00d2 92FBF3F3 		sdiv	r3, r2, r3
 155 00d6 1A46     		mov	r2, r3
 156 00d8 744B     		ldr	r3, .L40+12
 157 00da 1A60     		str	r2, [r3]
 148:srcc/system_msp432p401r.c ****         break;
 158              		.loc 1 148 0
 159 00dc 06E1     		b	.L2
 160              	.L6:
 149:srcc/system_msp432p401r.c ****     case CS_CTL1_SELM__REFOCLK:
 150:srcc/system_msp432p401r.c ****         if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
 161              		.loc 1 150 0
 162 00de 724B     		ldr	r3, .L40+8
 163 00e0 1B78     		ldrb	r3, [r3]
 164 00e2 DBB2     		uxtb	r3, r3
 165 00e4 002B     		cmp	r3, #0
 166 00e6 08D0     		beq	.L16
 151:srcc/system_msp432p401r.c ****         {
 152:srcc/system_msp432p401r.c ****             SystemCoreClock = (128000 / dividerValue);
 167              		.loc 1 152 0
 168 00e8 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 169 00ea 4FF4FA32 		mov	r2, #128000
 170 00ee 92FBF3F3 		sdiv	r3, r2, r3
 171 00f2 1A46     		mov	r2, r3
 172 00f4 6D4B     		ldr	r3, .L40+12
 173 00f6 1A60     		str	r2, [r3]
 153:srcc/system_msp432p401r.c ****         }
 154:srcc/system_msp432p401r.c ****         else
 155:srcc/system_msp432p401r.c ****         {
 156:srcc/system_msp432p401r.c ****             SystemCoreClock = (32000 / dividerValue);
 157:srcc/system_msp432p401r.c ****         }
 158:srcc/system_msp432p401r.c ****         break;
 174              		.loc 1 158 0
 175 00f8 F8E0     		b	.L2
 176              	.L16:
 156:srcc/system_msp432p401r.c ****         }
 177              		.loc 1 156 0
 178 00fa FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 179 00fc 4FF4FA42 		mov	r2, #32000
 180 0100 92FBF3F3 		sdiv	r3, r2, r3
 181 0104 1A46     		mov	r2, r3
 182 0106 694B     		ldr	r3, .L40+12
 183 0108 1A60     		str	r2, [r3]
 184              		.loc 1 158 0
 185 010a EFE0     		b	.L2
 186              	.L7:
 159:srcc/system_msp432p401r.c ****     case CS_CTL1_SELM__DCOCLK:
 160:srcc/system_msp432p401r.c ****         dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
 187              		.loc 1 160 0
 188 010c 644B     		ldr	r3, .L40
 189 010e 5B68     		ldr	r3, [r3, #4]
 190 0110 1BB2     		sxth	r3, r3
 191 0112 C3F30903 		ubfx	r3, r3, #0, #10
 192 0116 7B82     		strh	r3, [r7, #18]	@ movhi
 161:srcc/system_msp432p401r.c ****     
 162:srcc/system_msp432p401r.c ****         switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
 193              		.loc 1 162 0
 194 0118 614B     		ldr	r3, .L40
 195 011a 5B68     		ldr	r3, [r3, #4]
 196 011c 03F4E023 		and	r3, r3, #458752
 197 0120 B3F5003F 		cmp	r3, #131072
 198 0124 18D0     		beq	.L19
 199 0126 B3F5003F 		cmp	r3, #131072
 200 012a 05D8     		bhi	.L20
 201 012c 002B     		cmp	r3, #0
 202 012e 0DD0     		beq	.L21
 203 0130 B3F5803F 		cmp	r3, #65536
 204 0134 0DD0     		beq	.L22
 205 0136 1BE0     		b	.L18
 206              	.L20:
 207 0138 B3F5802F 		cmp	r3, #262144
 208 013c 12D0     		beq	.L23
 209 013e B3F5A02F 		cmp	r3, #327680
 210 0142 12D0     		beq	.L24
 211 0144 B3F5403F 		cmp	r3, #196608
 212 0148 09D0     		beq	.L25
 213 014a 11E0     		b	.L18
 214              	.L21:
 163:srcc/system_msp432p401r.c ****         {
 164:srcc/system_msp432p401r.c ****         case CS_CTL0_DCORSEL_0:
 165:srcc/system_msp432p401r.c ****             centeredFreq = 1500000;
 215              		.loc 1 165 0
 216 014c 584B     		ldr	r3, .L40+16
 217 014e 7B61     		str	r3, [r7, #20]
 166:srcc/system_msp432p401r.c ****             break;
 218              		.loc 1 166 0
 219 0150 11E0     		b	.L26
 220              	.L22:
 167:srcc/system_msp432p401r.c ****         case CS_CTL0_DCORSEL_1:
 168:srcc/system_msp432p401r.c ****             centeredFreq = 3000000;
 221              		.loc 1 168 0
 222 0152 584B     		ldr	r3, .L40+20
 223 0154 7B61     		str	r3, [r7, #20]
 169:srcc/system_msp432p401r.c ****             break;
 224              		.loc 1 169 0
 225 0156 0EE0     		b	.L26
 226              	.L19:
 170:srcc/system_msp432p401r.c ****         case CS_CTL0_DCORSEL_2:
 171:srcc/system_msp432p401r.c ****             centeredFreq = 6000000;
 227              		.loc 1 171 0
 228 0158 574B     		ldr	r3, .L40+24
 229 015a 7B61     		str	r3, [r7, #20]
 172:srcc/system_msp432p401r.c ****             break;
 230              		.loc 1 172 0
 231 015c 0BE0     		b	.L26
 232              	.L25:
 173:srcc/system_msp432p401r.c ****         case CS_CTL0_DCORSEL_3:
 174:srcc/system_msp432p401r.c ****             centeredFreq = 12000000;
 233              		.loc 1 174 0
 234 015e 574B     		ldr	r3, .L40+28
 235 0160 7B61     		str	r3, [r7, #20]
 175:srcc/system_msp432p401r.c ****             break;
 236              		.loc 1 175 0
 237 0162 08E0     		b	.L26
 238              	.L23:
 176:srcc/system_msp432p401r.c ****         case CS_CTL0_DCORSEL_4:
 177:srcc/system_msp432p401r.c ****             centeredFreq = 24000000;
 239              		.loc 1 177 0
 240 0164 564B     		ldr	r3, .L40+32
 241 0166 7B61     		str	r3, [r7, #20]
 178:srcc/system_msp432p401r.c ****             break;
 242              		.loc 1 178 0
 243 0168 05E0     		b	.L26
 244              	.L24:
 179:srcc/system_msp432p401r.c ****         case CS_CTL0_DCORSEL_5:
 180:srcc/system_msp432p401r.c ****             centeredFreq = 48000000;
 245              		.loc 1 180 0
 246 016a 564B     		ldr	r3, .L40+36
 247 016c 7B61     		str	r3, [r7, #20]
 181:srcc/system_msp432p401r.c ****             break;
 248              		.loc 1 181 0
 249 016e 02E0     		b	.L26
 250              	.L18:
 182:srcc/system_msp432p401r.c ****         default:
 183:srcc/system_msp432p401r.c ****         	centeredFreq=48000000;
 251              		.loc 1 183 0
 252 0170 544B     		ldr	r3, .L40+36
 253 0172 7B61     		str	r3, [r7, #20]
 184:srcc/system_msp432p401r.c ****         	break;
 254              		.loc 1 184 0
 255 0174 00BF     		nop
 256              	.L26:
 185:srcc/system_msp432p401r.c ****         }
 186:srcc/system_msp432p401r.c **** 
 187:srcc/system_msp432p401r.c ****         if(dcoTune == 0)
 257              		.loc 1 187 0
 258 0176 B7F91230 		ldrsh	r3, [r7, #18]
 259 017a 002B     		cmp	r3, #0
 260 017c 03D1     		bne	.L27
 188:srcc/system_msp432p401r.c ****         {
 189:srcc/system_msp432p401r.c ****             SystemCoreClock = centeredFreq;
 261              		.loc 1 189 0
 262 017e 4B4A     		ldr	r2, .L40+12
 263 0180 7B69     		ldr	r3, [r7, #20]
 264 0182 1360     		str	r3, [r2]
 190:srcc/system_msp432p401r.c ****         }
 191:srcc/system_msp432p401r.c ****         else
 192:srcc/system_msp432p401r.c ****         {
 193:srcc/system_msp432p401r.c **** 
 194:srcc/system_msp432p401r.c ****             if(dcoTune & 0x1000)
 195:srcc/system_msp432p401r.c ****             {
 196:srcc/system_msp432p401r.c ****                 dcoTune = dcoTune | 0xF000;
 197:srcc/system_msp432p401r.c ****             }
 198:srcc/system_msp432p401r.c **** 
 199:srcc/system_msp432p401r.c ****             if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
 200:srcc/system_msp432p401r.c ****             {
 201:srcc/system_msp432p401r.c ****                 dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04);
 202:srcc/system_msp432p401r.c ****                 calVal = TLV->DCOER_FCAL_RSEL04;
 203:srcc/system_msp432p401r.c ****             }
 204:srcc/system_msp432p401r.c ****             /* Internal Resistor */
 205:srcc/system_msp432p401r.c ****             else
 206:srcc/system_msp432p401r.c ****             {
 207:srcc/system_msp432p401r.c ****                 dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04);
 208:srcc/system_msp432p401r.c ****                 calVal = TLV->DCOIR_FCAL_RSEL04;
 209:srcc/system_msp432p401r.c ****             }
 210:srcc/system_msp432p401r.c **** 
 211:srcc/system_msp432p401r.c ****             SystemCoreClock = (uint32_t) ((centeredFreq)
 212:srcc/system_msp432p401r.c ****                                / (1
 213:srcc/system_msp432p401r.c ****                                     - ((dcoConst * dcoTune)
 214:srcc/system_msp432p401r.c ****                                             / (8 * (1 + dcoConst * (768 - calVal))))));
 215:srcc/system_msp432p401r.c ****         }
 216:srcc/system_msp432p401r.c ****         break;
 265              		.loc 1 216 0
 266 0184 B2E0     		b	.L2
 267              	.L27:
 194:srcc/system_msp432p401r.c ****             {
 268              		.loc 1 194 0
 269 0186 7B8A     		ldrh	r3, [r7, #18]
 270 0188 03F48053 		and	r3, r3, #4096
 271 018c 002B     		cmp	r3, #0
 272 018e 05D0     		beq	.L29
 196:srcc/system_msp432p401r.c ****             }
 273              		.loc 1 196 0
 274 0190 7B8A     		ldrh	r3, [r7, #18]	@ movhi
 275 0192 6FEA0353 		mvn	r3, r3, lsl #20
 276 0196 6FEA1353 		mvn	r3, r3, lsr #20
 277 019a 7B82     		strh	r3, [r7, #18]	@ movhi
 278              	.L29:
 199:srcc/system_msp432p401r.c ****             {
 279              		.loc 1 199 0
 280 019c 4A4B     		ldr	r3, .L40+40
 281 019e 1B78     		ldrb	r3, [r3]
 282 01a0 DBB2     		uxtb	r3, r3
 283 01a2 002B     		cmp	r3, #0
 284 01a4 06D0     		beq	.L30
 201:srcc/system_msp432p401r.c ****                 calVal = TLV->DCOER_FCAL_RSEL04;
 285              		.loc 1 201 0
 286 01a6 494B     		ldr	r3, .L40+44
 287 01a8 1B68     		ldr	r3, [r3]	@ float
 288 01aa FB61     		str	r3, [r7, #28]	@ float
 202:srcc/system_msp432p401r.c ****             }
 289              		.loc 1 202 0
 290 01ac 484B     		ldr	r3, .L40+48
 291 01ae DB6E     		ldr	r3, [r3, #108]
 292 01b0 BB61     		str	r3, [r7, #24]
 293 01b2 05E0     		b	.L31
 294              	.L30:
 207:srcc/system_msp432p401r.c ****                 calVal = TLV->DCOIR_FCAL_RSEL04;
 295              		.loc 1 207 0
 296 01b4 474B     		ldr	r3, .L40+52
 297 01b6 1B68     		ldr	r3, [r3]	@ float
 298 01b8 FB61     		str	r3, [r7, #28]	@ float
 208:srcc/system_msp432p401r.c ****             }
 299              		.loc 1 208 0
 300 01ba 454B     		ldr	r3, .L40+48
 301 01bc DB6C     		ldr	r3, [r3, #76]
 302 01be BB61     		str	r3, [r7, #24]
 303              	.L31:
 212:srcc/system_msp432p401r.c ****                                     - ((dcoConst * dcoTune)
 304              		.loc 1 212 0
 305 01c0 7B69     		ldr	r3, [r7, #20]
 306 01c2 07EE903A 		vmov	s15, r3	@ int
 307 01c6 F8EE676A 		vcvt.f32.u32	s13, s15
 213:srcc/system_msp432p401r.c ****                                             / (8 * (1 + dcoConst * (768 - calVal))))));
 308              		.loc 1 213 0
 309 01ca B7F91230 		ldrsh	r3, [r7, #18]
 310 01ce 07EE903A 		vmov	s15, r3	@ int
 311 01d2 B8EEE77A 		vcvt.f32.s32	s14, s15
 312 01d6 D7ED077A 		vldr.32	s15, [r7, #28]
 313 01da 27EE276A 		vmul.f32	s12, s14, s15
 214:srcc/system_msp432p401r.c ****         }
 314              		.loc 1 214 0
 315 01de BB69     		ldr	r3, [r7, #24]
 316 01e0 C3F54073 		rsb	r3, r3, #768
 317 01e4 07EE903A 		vmov	s15, r3	@ int
 318 01e8 B8EEE77A 		vcvt.f32.s32	s14, s15
 319 01ec D7ED077A 		vldr.32	s15, [r7, #28]
 320 01f0 67EE277A 		vmul.f32	s15, s14, s15
 321 01f4 B7EE007A 		vmov.f32	s14, #1.0e+0
 322 01f8 77EE877A 		vadd.f32	s15, s15, s14
 323 01fc B2EE007A 		vmov.f32	s14, #8.0e+0
 324 0200 27EE877A 		vmul.f32	s14, s15, s14
 325 0204 C6EE077A 		vdiv.f32	s15, s12, s14
 213:srcc/system_msp432p401r.c ****                                             / (8 * (1 + dcoConst * (768 - calVal))))));
 326              		.loc 1 213 0
 327 0208 B7EE007A 		vmov.f32	s14, #1.0e+0
 328 020c 37EE677A 		vsub.f32	s14, s14, s15
 212:srcc/system_msp432p401r.c ****                                     - ((dcoConst * dcoTune)
 329              		.loc 1 212 0
 330 0210 C6EE877A 		vdiv.f32	s15, s13, s14
 211:srcc/system_msp432p401r.c ****                                / (1
 331              		.loc 1 211 0
 332 0214 FCEEE77A 		vcvt.u32.f32	s15, s15
 333 0218 17EE902A 		vmov	r2, s15	@ int
 334 021c 234B     		ldr	r3, .L40+12
 335 021e 1A60     		str	r2, [r3]
 336              		.loc 1 216 0
 337 0220 64E0     		b	.L2
 338              	.L8:
 217:srcc/system_msp432p401r.c ****     case CS_CTL1_SELM__MODOSC:
 218:srcc/system_msp432p401r.c ****         SystemCoreClock = __MODCLK / dividerValue;
 339              		.loc 1 218 0
 340 0222 FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 341 0224 264A     		ldr	r2, .L40+32
 342 0226 92FBF3F3 		sdiv	r3, r2, r3
 343 022a 1A46     		mov	r2, r3
 344 022c 1F4B     		ldr	r3, .L40+12
 345 022e 1A60     		str	r2, [r3]
 219:srcc/system_msp432p401r.c ****         break;
 346              		.loc 1 219 0
 347 0230 5CE0     		b	.L2
 348              	.L9:
 220:srcc/system_msp432p401r.c ****     case CS_CTL1_SELM__HFXTCLK:
 221:srcc/system_msp432p401r.c ****         if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
 349              		.loc 1 221 0
 350 0232 294B     		ldr	r3, .L40+56
 351 0234 1B78     		ldrb	r3, [r3]
 352 0236 DBB2     		uxtb	r3, r3
 353 0238 002B     		cmp	r3, #0
 354 023a 4FD0     		beq	.L32
 222:srcc/system_msp432p401r.c ****         {
 223:srcc/system_msp432p401r.c ****             // Clear interrupt flag
 224:srcc/system_msp432p401r.c ****             CS->KEY = CS_KEY_VAL;
 355              		.loc 1 224 0
 356 023c 184B     		ldr	r3, .L40
 357 023e 46F65A12 		movw	r2, #26970
 358 0242 1A60     		str	r2, [r3]
 225:srcc/system_msp432p401r.c ****             CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
 359              		.loc 1 225 0
 360 0244 164B     		ldr	r3, .L40
 361 0246 1B6D     		ldr	r3, [r3, #80]
 362 0248 154A     		ldr	r2, .L40
 363 024a 43F00203 		orr	r3, r3, #2
 364 024e 1365     		str	r3, [r2, #80]
 226:srcc/system_msp432p401r.c ****             CS->KEY = 1;
 365              		.loc 1 226 0
 366 0250 134B     		ldr	r3, .L40
 367 0252 0122     		movs	r2, #1
 368 0254 1A60     		str	r2, [r3]
 227:srcc/system_msp432p401r.c **** 
 228:srcc/system_msp432p401r.c ****             if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
 369              		.loc 1 228 0
 370 0256 204B     		ldr	r3, .L40+56
 371 0258 1B78     		ldrb	r3, [r3]
 372 025a DBB2     		uxtb	r3, r3
 373 025c 002B     		cmp	r3, #0
 374 025e 16D0     		beq	.L33
 229:srcc/system_msp432p401r.c ****             {
 230:srcc/system_msp432p401r.c ****                 if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
 375              		.loc 1 230 0
 376 0260 114B     		ldr	r3, .L40+8
 377 0262 1B78     		ldrb	r3, [r3]
 378 0264 DBB2     		uxtb	r3, r3
 379 0266 002B     		cmp	r3, #0
 380 0268 08D0     		beq	.L34
 231:srcc/system_msp432p401r.c ****                 {
 232:srcc/system_msp432p401r.c ****                     SystemCoreClock = (128000 / dividerValue);
 381              		.loc 1 232 0
 382 026a FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 383 026c 4FF4FA32 		mov	r2, #128000
 384 0270 92FBF3F3 		sdiv	r3, r2, r3
 385 0274 1A46     		mov	r2, r3
 386 0276 0D4B     		ldr	r3, .L40+12
 387 0278 1A60     		str	r2, [r3]
 233:srcc/system_msp432p401r.c ****                 }
 234:srcc/system_msp432p401r.c ****                 else
 235:srcc/system_msp432p401r.c ****                 {
 236:srcc/system_msp432p401r.c ****                     SystemCoreClock = (32000 / dividerValue);
 237:srcc/system_msp432p401r.c ****                 }
 238:srcc/system_msp432p401r.c ****             }
 239:srcc/system_msp432p401r.c ****             else
 240:srcc/system_msp432p401r.c ****             {
 241:srcc/system_msp432p401r.c ****                 SystemCoreClock = __HFXT / dividerValue;
 242:srcc/system_msp432p401r.c ****             }
 243:srcc/system_msp432p401r.c ****         }
 244:srcc/system_msp432p401r.c ****         else
 245:srcc/system_msp432p401r.c ****         {
 246:srcc/system_msp432p401r.c ****             SystemCoreClock = __HFXT / dividerValue;
 247:srcc/system_msp432p401r.c ****         }
 248:srcc/system_msp432p401r.c ****         break;
 388              		.loc 1 248 0
 389 027a 36E0     		b	.L39
 390              	.L34:
 236:srcc/system_msp432p401r.c ****                 }
 391              		.loc 1 236 0
 392 027c FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 393 027e 4FF4FA42 		mov	r2, #32000
 394 0282 92FBF3F3 		sdiv	r3, r2, r3
 395 0286 1A46     		mov	r2, r3
 396 0288 084B     		ldr	r3, .L40+12
 397 028a 1A60     		str	r2, [r3]
 398              		.loc 1 248 0
 399 028c 2DE0     		b	.L39
 400              	.L33:
 241:srcc/system_msp432p401r.c ****             }
 401              		.loc 1 241 0
 402 028e FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 403 0290 0C4A     		ldr	r2, .L40+36
 404 0292 92FBF3F3 		sdiv	r3, r2, r3
 405 0296 1A46     		mov	r2, r3
 406 0298 044B     		ldr	r3, .L40+12
 407 029a 1A60     		str	r2, [r3]
 408              		.loc 1 248 0
 409 029c 25E0     		b	.L39
 410              	.L41:
 411 029e 00BF     		.align	2
 412              	.L40:
 413 02a0 00040140 		.word	1073808384
 414 02a4 00892042 		.word	1109428480
 415 02a8 3C862042 		.word	1109427772
 416 02ac 00000000 		.word	SystemCoreClock
 417 02b0 60E31600 		.word	1500000
 418 02b4 C0C62D00 		.word	3000000
 419 02b8 808D5B00 		.word	6000000
 420 02bc 001BB700 		.word	12000000
 421 02c0 00366E01 		.word	24000000
 422 02c4 006CDC02 		.word	48000000
 423 02c8 D8802042 		.word	1109426392
 424 02cc 84102000 		.word	2101380
 425 02d0 00102000 		.word	2101248
 426 02d4 64102000 		.word	2101348
 427 02d8 04892042 		.word	1109428484
 428              	.L32:
 246:srcc/system_msp432p401r.c ****         }
 429              		.loc 1 246 0
 430 02dc FB7A     		ldrb	r3, [r7, #11]	@ zero_extendqisi2
 431 02de 064A     		ldr	r2, .L42
 432 02e0 92FBF3F3 		sdiv	r3, r2, r3
 433 02e4 1A46     		mov	r2, r3
 434 02e6 054B     		ldr	r3, .L42+4
 435 02e8 1A60     		str	r2, [r3]
 436              	.L39:
 437              		.loc 1 248 0
 438 02ea 00BF     		nop
 439              	.L2:
 440              	.L38:
 249:srcc/system_msp432p401r.c ****     }
 250:srcc/system_msp432p401r.c **** }
 441              		.loc 1 250 0
 442 02ec 00BF     		nop
 443 02ee 2437     		adds	r7, r7, #36
 444              		.cfi_def_cfa_offset 4
 445 02f0 BD46     		mov	sp, r7
 446              		.cfi_def_cfa_register 13
 447              		@ sp needed
 448 02f2 5DF8047B 		ldr	r7, [sp], #4
 449              		.cfi_restore 7
 450              		.cfi_def_cfa_offset 0
 451 02f6 7047     		bx	lr
 452              	.L43:
 453              		.align	2
 454              	.L42:
 455 02f8 006CDC02 		.word	48000000
 456 02fc 00000000 		.word	SystemCoreClock
 457              		.cfi_endproc
 458              	.LFE123:
 460              		.align	1
 461              		.global	SystemInit
 462              		.syntax unified
 463              		.thumb
 464              		.thumb_func
 465              		.fpu fpv4-sp-d16
 467              	SystemInit:
 468              	.LFB124:
 251:srcc/system_msp432p401r.c **** 
 252:srcc/system_msp432p401r.c **** /**
 253:srcc/system_msp432p401r.c ****  * Initialize the system
 254:srcc/system_msp432p401r.c ****  *
 255:srcc/system_msp432p401r.c ****  * @param  none
 256:srcc/system_msp432p401r.c ****  * @return none
 257:srcc/system_msp432p401r.c ****  *
 258:srcc/system_msp432p401r.c ****  * @brief  Setup the microcontroller system.
 259:srcc/system_msp432p401r.c ****  *
 260:srcc/system_msp432p401r.c ****  * Performs the following initialization steps:
 261:srcc/system_msp432p401r.c ****  *     1. Enables the FPU
 262:srcc/system_msp432p401r.c ****  *     2. Halts the WDT if requested
 263:srcc/system_msp432p401r.c ****  *     3. Enables all SRAM banks
 264:srcc/system_msp432p401r.c ****  *     4. Sets up power regulator and VCORE
 265:srcc/system_msp432p401r.c ****  *     5. Enable Flash wait states if needed
 266:srcc/system_msp432p401r.c ****  *     6. Change MCLK to desired frequency
 267:srcc/system_msp432p401r.c ****  *     7. Enable Flash read buffering
 268:srcc/system_msp432p401r.c ****  */
 269:srcc/system_msp432p401r.c **** void SystemInit(void)
 270:srcc/system_msp432p401r.c **** {
 469              		.loc 1 270 0
 470              		.cfi_startproc
 471              		@ args = 0, pretend = 0, frame = 0
 472              		@ frame_needed = 1, uses_anonymous_args = 0
 473              		@ link register save eliminated.
 474 0300 80B4     		push	{r7}
 475              		.cfi_def_cfa_offset 4
 476              		.cfi_offset 7, -4
 477 0302 00AF     		add	r7, sp, #0
 478              		.cfi_def_cfa_register 7
 271:srcc/system_msp432p401r.c ****     // Enable FPU if used
 272:srcc/system_msp432p401r.c ****     #if (__FPU_USED == 1)                                  // __FPU_USED is defined in core_cm4.h
 273:srcc/system_msp432p401r.c ****     SCB->CPACR |= ((3UL << 10 * 2) |                       // Set CP10 Full Access
 479              		.loc 1 273 0
 480 0304 294B     		ldr	r3, .L47
 481 0306 D3F88830 		ldr	r3, [r3, #136]
 482 030a 284A     		ldr	r2, .L47
 483 030c 43F47003 		orr	r3, r3, #15728640
 484 0310 C2F88830 		str	r3, [r2, #136]
 274:srcc/system_msp432p401r.c ****                    (3UL << 11 * 2));                       // Set CP11 Full Access
 275:srcc/system_msp432p401r.c ****     #endif
 276:srcc/system_msp432p401r.c **** 
 277:srcc/system_msp432p401r.c ****     #if (__HALT_WDT == 1)
 278:srcc/system_msp432p401r.c ****     WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD;            // Halt the WDT
 485              		.loc 1 278 0
 486 0314 264B     		ldr	r3, .L47+4
 487 0316 4FF4B542 		mov	r2, #23168
 488 031a 9A81     		strh	r2, [r3, #12]	@ movhi
 279:srcc/system_msp432p401r.c ****     #endif
 280:srcc/system_msp432p401r.c **** 
 281:srcc/system_msp432p401r.c ****     SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN;      // Enable all SRAM banks
 489              		.loc 1 281 0
 490 031c 254B     		ldr	r3, .L47+8
 491 031e 8022     		movs	r2, #128
 492 0320 5A61     		str	r2, [r3, #20]
 282:srcc/system_msp432p401r.c **** 
 283:srcc/system_msp432p401r.c ****     #if (__SYSTEM_CLOCK == 1500000)                        // 1.5 MHz
 284:srcc/system_msp432p401r.c ****     // Default VCORE is LDO VCORE0 so no change necessary
 285:srcc/system_msp432p401r.c **** 
 286:srcc/system_msp432p401r.c ****     // Switches LDO VCORE0 to DCDC VCORE0 if requested
 287:srcc/system_msp432p401r.c ****     #if __REGULATOR
 288:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 289:srcc/system_msp432p401r.c ****     PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
 290:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 291:srcc/system_msp432p401r.c ****     #endif
 292:srcc/system_msp432p401r.c **** 
 293:srcc/system_msp432p401r.c ****     // No flash wait states necessary
 294:srcc/system_msp432p401r.c **** 
 295:srcc/system_msp432p401r.c ****     // DCO = 1.5 MHz; MCLK = source
 296:srcc/system_msp432p401r.c ****     CS->KEY = CS_KEY_VAL;                                  // Unlock CS module for register access
 297:srcc/system_msp432p401r.c ****     CS->CTL0 = CS_CTL0_DCORSEL_0;                          // Set DCO to 1.5MHz
 298:srcc/system_msp432p401r.c ****     CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;  
 299:srcc/system_msp432p401r.c **** 	                                                       // Select MCLK as DCO source
 300:srcc/system_msp432p401r.c ****     CS->KEY = 0;
 301:srcc/system_msp432p401r.c **** 
 302:srcc/system_msp432p401r.c ****     // Set Flash Bank read buffering
 303:srcc/system_msp432p401r.c ****     FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
 304:srcc/system_msp432p401r.c ****     FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
 305:srcc/system_msp432p401r.c **** 
 306:srcc/system_msp432p401r.c ****     #elif (__SYSTEM_CLOCK == 3000000)                      // 3 MHz
 307:srcc/system_msp432p401r.c ****     // Default VCORE is LDO VCORE0 so no change necessary
 308:srcc/system_msp432p401r.c **** 
 309:srcc/system_msp432p401r.c ****     // Switches LDO VCORE0 to DCDC VCORE0 if requested
 310:srcc/system_msp432p401r.c ****     #if __REGULATOR
 311:srcc/system_msp432p401r.c ****     while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
 312:srcc/system_msp432p401r.c ****     PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
 313:srcc/system_msp432p401r.c ****     while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
 314:srcc/system_msp432p401r.c ****     #endif
 315:srcc/system_msp432p401r.c **** 
 316:srcc/system_msp432p401r.c ****     // No flash wait states necessary
 317:srcc/system_msp432p401r.c **** 
 318:srcc/system_msp432p401r.c ****     // DCO = 3 MHz; MCLK = source
 319:srcc/system_msp432p401r.c ****     CS->KEY = CS_KEY_VAL;                                  // Unlock CS module for register access
 320:srcc/system_msp432p401r.c ****     CS->CTL0 = CS_CTL0_DCORSEL_1;                          // Set DCO to 1.5MHz
 321:srcc/system_msp432p401r.c ****     CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;  
 322:srcc/system_msp432p401r.c **** 	                                                       // Select MCLK as DCO source
 323:srcc/system_msp432p401r.c ****     CS->KEY = 0;
 324:srcc/system_msp432p401r.c **** 
 325:srcc/system_msp432p401r.c ****     // Set Flash Bank read buffering
 326:srcc/system_msp432p401r.c ****     FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
 327:srcc/system_msp432p401r.c ****     FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
 328:srcc/system_msp432p401r.c **** 
 329:srcc/system_msp432p401r.c ****     #elif (__SYSTEM_CLOCK == 12000000)                     // 12 MHz
 330:srcc/system_msp432p401r.c ****     // Default VCORE is LDO VCORE0 so no change necessary
 331:srcc/system_msp432p401r.c **** 
 332:srcc/system_msp432p401r.c ****     // Switches LDO VCORE0 to DCDC VCORE0 if requested
 333:srcc/system_msp432p401r.c ****     #if __REGULATOR
 334:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 335:srcc/system_msp432p401r.c ****     PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
 336:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 337:srcc/system_msp432p401r.c ****     #endif
 338:srcc/system_msp432p401r.c **** 
 339:srcc/system_msp432p401r.c ****     // No flash wait states necessary
 340:srcc/system_msp432p401r.c **** 
 341:srcc/system_msp432p401r.c ****     // DCO = 12 MHz; MCLK = source
 342:srcc/system_msp432p401r.c ****     CS->KEY = CS_KEY_VAL;                                  // Unlock CS module for register access
 343:srcc/system_msp432p401r.c ****     CS->CTL0 = CS_CTL0_DCORSEL_3;                          // Set DCO to 12MHz
 344:srcc/system_msp432p401r.c ****     CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;  
 345:srcc/system_msp432p401r.c **** 	                                                       // Select MCLK as DCO source
 346:srcc/system_msp432p401r.c ****     CS->KEY = 0;
 347:srcc/system_msp432p401r.c **** 
 348:srcc/system_msp432p401r.c ****     // Set Flash Bank read buffering
 349:srcc/system_msp432p401r.c ****     FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
 350:srcc/system_msp432p401r.c ****     FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
 351:srcc/system_msp432p401r.c **** 
 352:srcc/system_msp432p401r.c ****     #elif (__SYSTEM_CLOCK == 24000000)                     // 24 MHz
 353:srcc/system_msp432p401r.c ****     // Default VCORE is LDO VCORE0 so no change necessary
 354:srcc/system_msp432p401r.c **** 
 355:srcc/system_msp432p401r.c ****     // Switches LDO VCORE0 to DCDC VCORE0 if requested
 356:srcc/system_msp432p401r.c ****     #if __REGULATOR
 357:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 358:srcc/system_msp432p401r.c ****     PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
 359:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 360:srcc/system_msp432p401r.c ****     #endif
 361:srcc/system_msp432p401r.c **** 
 362:srcc/system_msp432p401r.c ****     // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
 363:srcc/system_msp432p401r.c ****     FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WA
 364:srcc/system_msp432p401r.c ****     FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WA
 365:srcc/system_msp432p401r.c **** 
 366:srcc/system_msp432p401r.c ****     // DCO = 24 MHz; MCLK = source
 367:srcc/system_msp432p401r.c ****     CS->KEY = CS_KEY_VAL;                                  // Unlock CS module for register access
 368:srcc/system_msp432p401r.c ****     CS->CTL0 = CS_CTL0_DCORSEL_4;                          // Set DCO to 24MHz
 369:srcc/system_msp432p401r.c ****     CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;  
 370:srcc/system_msp432p401r.c **** 	                                                       // Select MCLK as DCO source
 371:srcc/system_msp432p401r.c ****     CS->KEY = 0;
 372:srcc/system_msp432p401r.c **** 
 373:srcc/system_msp432p401r.c ****     // Set Flash Bank read buffering
 374:srcc/system_msp432p401r.c ****     FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
 375:srcc/system_msp432p401r.c ****     FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
 376:srcc/system_msp432p401r.c **** 
 377:srcc/system_msp432p401r.c ****     #elif (__SYSTEM_CLOCK == 48000000)                     // 48 MHz
 378:srcc/system_msp432p401r.c ****     // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
 379:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 493              		.loc 1 379 0
 494 0322 00BF     		nop
 495              	.L45:
 496              		.loc 1 379 0 is_stmt 0
 497 0324 244B     		ldr	r3, .L47+12
 498 0326 5B68     		ldr	r3, [r3, #4]
 499 0328 03F48073 		and	r3, r3, #256
 500 032c 002B     		cmp	r3, #0
 501 032e F9D1     		bne	.L45
 380:srcc/system_msp432p401r.c ****     PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
 502              		.loc 1 380 0 is_stmt 1
 503 0330 214B     		ldr	r3, .L47+12
 504 0332 224A     		ldr	r2, .L47+16
 505 0334 1A60     		str	r2, [r3]
 381:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 506              		.loc 1 381 0
 507 0336 00BF     		nop
 508              	.L46:
 509              		.loc 1 381 0 is_stmt 0
 510 0338 1F4B     		ldr	r3, .L47+12
 511 033a 5B68     		ldr	r3, [r3, #4]
 512 033c 03F48073 		and	r3, r3, #256
 513 0340 002B     		cmp	r3, #0
 514 0342 F9D1     		bne	.L46
 382:srcc/system_msp432p401r.c **** 
 383:srcc/system_msp432p401r.c ****     // Switches LDO VCORE1 to DCDC VCORE1 if requested
 384:srcc/system_msp432p401r.c ****     #if __REGULATOR
 385:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 386:srcc/system_msp432p401r.c ****     PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
 387:srcc/system_msp432p401r.c ****     while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
 388:srcc/system_msp432p401r.c ****     #endif
 389:srcc/system_msp432p401r.c **** 
 390:srcc/system_msp432p401r.c ****     // 2 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
 391:srcc/system_msp432p401r.c ****     FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WA
 515              		.loc 1 391 0 is_stmt 1
 516 0344 1E4B     		ldr	r3, .L47+20
 517 0346 1B69     		ldr	r3, [r3, #16]
 518 0348 23F47043 		bic	r3, r3, #61440
 519 034c 1C4A     		ldr	r2, .L47+20
 520 034e 43F40053 		orr	r3, r3, #8192
 521 0352 1361     		str	r3, [r2, #16]
 392:srcc/system_msp432p401r.c ****     FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WA
 522              		.loc 1 392 0
 523 0354 1A4B     		ldr	r3, .L47+20
 524 0356 5B69     		ldr	r3, [r3, #20]
 525 0358 23F47043 		bic	r3, r3, #61440
 526 035c 184A     		ldr	r2, .L47+20
 527 035e 43F40053 		orr	r3, r3, #8192
 528 0362 5361     		str	r3, [r2, #20]
 393:srcc/system_msp432p401r.c **** 
 394:srcc/system_msp432p401r.c ****     // DCO = 48 MHz; MCLK = source
 395:srcc/system_msp432p401r.c ****     CS->KEY = CS_KEY_VAL;                                  // Unlock CS module for register access
 529              		.loc 1 395 0
 530 0364 174B     		ldr	r3, .L47+24
 531 0366 46F65A12 		movw	r2, #26970
 532 036a 1A60     		str	r2, [r3]
 396:srcc/system_msp432p401r.c ****     CS->CTL0 = CS_CTL0_DCORSEL_5;                          // Set DCO to 48MHz
 533              		.loc 1 396 0
 534 036c 154B     		ldr	r3, .L47+24
 535 036e 4FF4A022 		mov	r2, #327680
 536 0372 5A60     		str	r2, [r3, #4]
 397:srcc/system_msp432p401r.c ****     CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;  
 537              		.loc 1 397 0
 538 0374 134B     		ldr	r3, .L47+24
 539 0376 9B68     		ldr	r3, [r3, #8]
 540 0378 23F00713 		bic	r3, r3, #458759
 541 037c 114A     		ldr	r2, .L47+24
 542 037e 43F00303 		orr	r3, r3, #3
 543 0382 9360     		str	r3, [r2, #8]
 398:srcc/system_msp432p401r.c **** 	                                                       // Select MCLK as DCO source
 399:srcc/system_msp432p401r.c ****     CS->KEY = 0;
 544              		.loc 1 399 0
 545 0384 0F4B     		ldr	r3, .L47+24
 546 0386 0022     		movs	r2, #0
 547 0388 1A60     		str	r2, [r3]
 400:srcc/system_msp432p401r.c **** 
 401:srcc/system_msp432p401r.c ****     // Set Flash Bank read buffering
 402:srcc/system_msp432p401r.c ****     FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
 548              		.loc 1 402 0
 549 038a 0D4B     		ldr	r3, .L47+20
 550 038c 1B69     		ldr	r3, [r3, #16]
 551 038e 0C4A     		ldr	r2, .L47+20
 552 0390 43F03003 		orr	r3, r3, #48
 553 0394 1361     		str	r3, [r2, #16]
 403:srcc/system_msp432p401r.c ****     FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
 554              		.loc 1 403 0
 555 0396 0A4B     		ldr	r3, .L47+20
 556 0398 5B69     		ldr	r3, [r3, #20]
 557 039a 094A     		ldr	r2, .L47+20
 558 039c 43F03003 		orr	r3, r3, #48
 559 03a0 5361     		str	r3, [r2, #20]
 404:srcc/system_msp432p401r.c ****     #endif
 405:srcc/system_msp432p401r.c **** 
 406:srcc/system_msp432p401r.c **** }
 560              		.loc 1 406 0
 561 03a2 00BF     		nop
 562 03a4 BD46     		mov	sp, r7
 563              		.cfi_def_cfa_register 13
 564              		@ sp needed
 565 03a6 5DF8047B 		ldr	r7, [sp], #4
 566              		.cfi_restore 7
 567              		.cfi_def_cfa_offset 0
 568 03aa 7047     		bx	lr
 569              	.L48:
 570              		.align	2
 571              	.L47:
 572 03ac 00ED00E0 		.word	-536810240
 573 03b0 00480040 		.word	1073760256
 574 03b4 003004E0 		.word	-536596480
 575 03b8 00000140 		.word	1073807360
 576 03bc 01005A69 		.word	1767505921
 577 03c0 00100140 		.word	1073811456
 578 03c4 00040140 		.word	1073808384
 579              		.cfi_endproc
 580              	.LFE124:
 582              	.Letext0:
 583              		.file 2 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 584              		.file 3 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 585              		.file 4 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH09-Flash\
 586              		.file 5 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH09-Flash\
 587              		.file 6 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH09-Flash\
DEFINED SYMBOLS
                            *ABS*:00000000 system_msp432p401r.c
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:22     .data:00000000 SystemCoreClock
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:19     .data:00000000 $d
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:25     .text:00000000 $t
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:32     .text:00000000 SystemCoreClockUpdate
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:71     .text:00000034 $d
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:77     .text:0000004c $t
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:413    .text:000002a0 $d
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:430    .text:000002dc $t
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:455    .text:000002f8 $d
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:460    .text:00000300 $t
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:467    .text:00000300 SystemInit
C:\Users\lenovo\AppData\Local\Temp\ccn6q30F.s:572    .text:000003ac $d

NO UNDEFINED SYMBOLS
