   1              		.cpu cortex-m4
   2              		.eabi_attribute 27, 1
   3              		.eabi_attribute 28, 1
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 6
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"systick.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.align	1
  18              		.syntax unified
  19              		.thumb
  20              		.thumb_func
  21              		.fpu fpv4-sp-d16
  23              	NVIC_SetPriority:
  24              	.LFB114:
  25              		.file 1 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH07-TIMER\
   1:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**************************************************************************//**
   2:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  * @file     core_cm4.h
   3:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
   4:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  * @version  V4.30
   5:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  * @date     20. October 2015
   6:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
   7:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
   8:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
   9:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    All rights reserved.
  10:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    Redistribution and use in source and binary forms, with or without
  11:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    modification, are permitted provided that the following conditions are met:
  12:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    - Redistributions of source code must retain the above copyright
  13:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      notice, this list of conditions and the following disclaimer.
  14:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    - Redistributions in binary form must reproduce the above copyright
  15:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      notice, this list of conditions and the following disclaimer in the
  16:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      documentation and/or other materials provided with the distribution.
  17:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    - Neither the name of ARM nor the names of its contributors may be used
  18:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      to endorse or promote products derived from this software without
  19:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      specific prior written permission.
  20:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    *
  21:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  25:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    POSSIBILITY OF SUCH DAMAGE.
  32:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    ---------------------------------------------------------------------------*/
  33:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  34:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  35:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if   defined ( __ICCARM__ )
  36:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  #pragma system_include         /* treat file as system include file for MISRA check */
  37:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  38:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #pragma clang system_header   /* treat file as system include file */
  39:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
  40:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  41:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
  42:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORE_CM4_H_GENERIC
  43:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  44:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #include <stdint.h>
  45:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  46:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
  47:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  extern "C" {
  48:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
  49:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  50:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
  51:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  52:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   CMSIS violates the following MISRA-C:2004 rules:
  53:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  54:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  55:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      Function definitions in header files are used to allow 'inlining'.
  56:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  57:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  58:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      Unions are used for effective representation of core registers.
  59:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  60:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  61:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****      Function-like macros are used to allow more efficient code.
  62:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
  63:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  64:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  65:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
  66:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  *                 CMSIS definitions
  67:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
  68:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
  69:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup Cortex_M4
  70:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
  71:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
  72:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  73:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*  CMSIS CM4 definitions */
  74:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS H
  75:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS H
  76:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
  77:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****                                     __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL versi
  78:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  79:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core *
  80:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  81:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  82:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if   defined ( __CC_ARM )
  83:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
  84:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
  85:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static __inline
  86:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  87:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  88:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
  89:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
  90:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static __inline
  91:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  92:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __GNUC__ )
  93:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for GNU Comp
  94:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for GNU C
  95:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
  96:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
  97:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __ICCARM__ )
  98:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for IAR Comp
  99:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for IAR C
 100:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 101:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 102:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TMS470__ )
 103:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TI CCS C
 104:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 105:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 106:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TASKING__ )
 107:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TASKING 
 108:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for TASKI
 109:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 110:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 111:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __CSMC__ )
 112:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __packed
 113:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Co
 114:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                    /*!< inline keyword for COSMIC
 115:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 116:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 117:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #else
 118:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #error Unknown compiler
 119:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 120:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 121:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
 122:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
 123:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** */
 124:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if defined ( __CC_ARM )
 125:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __TARGET_FPU_VFP
 126:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 127:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 128:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 129:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 130:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 131:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 132:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 133:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 134:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 135:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 136:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
 137:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __ARM_PCS_VFP
 138:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1)
 139:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 140:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 141:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
 142:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 143:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 144:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 145:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 146:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 147:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 148:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __GNUC__ )
 149:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
 150:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 151:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 152:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 153:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 154:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 155:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 156:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 157:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 158:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 159:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 160:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __ICCARM__ )
 161:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __ARMVFP__
 162:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 163:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 164:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 165:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 166:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 167:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 168:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 169:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 170:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 171:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 172:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TMS470__ )
 173:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __TI_VFP_SUPPORT__
 174:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 175:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 176:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 177:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 178:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 179:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 180:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 181:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 182:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 183:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 184:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TASKING__ )
 185:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __FPU_VFP__
 186:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 187:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 188:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 189:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 190:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 191:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 192:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 193:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 194:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 195:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 196:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __CSMC__ )
 197:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #if ( __CSMC__ & 0x400U)
 198:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 199:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 200:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 201:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 202:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 203:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 204:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 205:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 206:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 207:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 208:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 209:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 210:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmInstr.h"                /* Core Instruction Access */
 211:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmFunc.h"                 /* Core Function Access */
 212:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
 213:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 214:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 215:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
 216:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 217:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 218:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
 219:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 220:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CMSIS_GENERIC
 221:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 222:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
 223:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
 224:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 225:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 226:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  extern "C" {
 227:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 228:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 229:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* check device defines and use defaults */
 230:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
 231:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __CM4_REV
 232:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __CM4_REV               0x0000U
 233:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__CM4_REV not defined in device header file; using default!"
 234:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 235:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 236:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __FPU_PRESENT
 237:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_PRESENT             0U
 238:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
 239:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 240:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 241:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __MPU_PRESENT
 242:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __MPU_PRESENT             0U
 243:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
 244:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 245:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 246:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __NVIC_PRIO_BITS
 247:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __NVIC_PRIO_BITS          4U
 248:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 249:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 250:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 251:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __Vendor_SysTickConfig
 252:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __Vendor_SysTickConfig    0U
 253:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 254:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 255:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 256:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 257:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
 258:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 259:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 260:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 261:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     <strong>IO Type Qualifiers</strong> are used
 262:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     \li to specify the access to peripheral variables.
 263:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     \li for automatic generation of peripheral register debug information.
 264:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** */
 265:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 266:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 267:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #else
 268:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 269:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 270:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 271:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 272:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 273:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* following defines should be used for structure members */
 274:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 275:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 276:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 277:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 278:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group Cortex_M4 */
 279:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 280:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 281:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 282:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
 283:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  *                 Register Abstraction
 284:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   Core Register contain:
 285:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Register
 286:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core NVIC Register
 287:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SCB Register
 288:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SysTick Register
 289:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Debug Register
 290:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core MPU Register
 291:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core FPU Register
 292:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
 293:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 294:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 295:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 296:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** */
 297:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 298:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 299:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
 300:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 301:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Core Register type definitions.
 302:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 303:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 304:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 305:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 306:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 307:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 308:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 309:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 310:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 311:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 312:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
 313:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 314:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
 315:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 316:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 317:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 318:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 319:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 320:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 321:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 322:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } APSR_Type;
 323:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 324:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* APSR Register Definitions */
 325:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 326:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 327:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 328:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 329:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 330:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 331:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 332:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 333:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 334:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 335:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 336:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 337:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
 338:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
 339:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 340:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
 341:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
 342:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 343:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 344:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 345:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 346:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 347:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 348:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 349:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 350:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 351:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 352:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 353:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 354:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 355:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } IPSR_Type;
 356:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 357:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* IPSR Register Definitions */
 358:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 359:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 360:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 361:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 362:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 363:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 364:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 365:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 366:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 367:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 368:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 369:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 370:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
 371:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 372:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
 373:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 374:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
 375:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 376:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 377:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 378:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 379:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 380:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 381:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 382:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } xPSR_Type;
 383:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 384:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* xPSR Register Definitions */
 385:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 386:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 387:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 388:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 389:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 390:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 391:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 392:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 393:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 394:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 395:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 396:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 397:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
 398:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
 399:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 400:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_IT_Pos                        25U                                            /*!< xPSR
 401:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR
 402:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 403:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 404:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 405:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 406:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
 407:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
 408:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 409:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 410:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 411:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 412:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 413:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 414:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Control Registers (CONTROL).
 415:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 416:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 417:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 418:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 419:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 420:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
 421:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 422:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
 423:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
 424:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 425:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 426:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } CONTROL_Type;
 427:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 428:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* CONTROL Register Definitions */
 429:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
 430:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
 431:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 432:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 433:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 434:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 435:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
 436:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
 437:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 438:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_CORE */
 439:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 440:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 441:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 442:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
 443:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 444:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Type definitions for the NVIC Registers
 445:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 446:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 447:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 448:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 449:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 450:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 451:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 452:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 453:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 454:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[24U];
 455:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 456:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RSERVED1[24U];
 457:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 458:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[24U];
 459:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 460:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[24U];
 461:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
 462:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[56U];
 463:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
 464:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[644U];
 465:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
 466:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }  NVIC_Type;
 467:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 468:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
 469:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
 470:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
 471:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 472:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_NVIC */
 473:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 474:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 475:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 476:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 477:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 478:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Control Block Registers
 479:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 480:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 481:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 482:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 483:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Control Block (SCB).
 484:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 485:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 486:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 487:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 488:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 489:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 490:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 491:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 492:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 493:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
 494:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 495:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
 496:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
 497:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
 498:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
 499:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
 500:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
 501:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
 502:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
 503:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
 504:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
 505:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
 506:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[5U];
 507:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
 508:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } SCB_Type;
 509:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 510:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB CPUID Register Definitions */
 511:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 512:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 513:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 514:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 515:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 516:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 517:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 518:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 519:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 520:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 521:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 522:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 523:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 524:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 525:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 526:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
 527:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 528:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 529:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 530:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 531:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 532:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 533:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 534:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 535:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 536:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 537:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 538:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 539:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 540:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 541:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 542:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 543:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 544:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 545:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 546:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 547:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 548:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 549:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 550:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 551:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
 552:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
 553:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 554:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 555:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 556:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 557:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
 558:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
 559:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
 560:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 561:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 562:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 563:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 564:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 565:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 566:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 567:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 568:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 569:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 570:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 571:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
 572:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
 573:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 574:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 575:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 576:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 577:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 578:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 579:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 580:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
 581:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
 582:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 583:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB System Control Register Definitions */
 584:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 585:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 586:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 587:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 588:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 589:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 590:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 591:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 592:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 593:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Configuration Control Register Definitions */
 594:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 595:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 596:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 597:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
 598:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
 599:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 600:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
 601:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
 602:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 603:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 604:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 605:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 606:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
 607:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
 608:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 609:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
 610:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
 611:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 612:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
 613:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
 614:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
 615:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 616:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
 617:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
 618:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 619:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
 620:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
 621:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 622:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 623:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 624:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 625:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
 626:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
 627:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 628:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
 629:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
 630:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 631:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
 632:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
 633:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 634:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
 635:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
 636:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 637:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
 638:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
 639:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 640:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
 641:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
 642:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 643:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
 644:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
 645:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 646:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
 647:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
 648:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 649:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
 650:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
 651:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 652:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
 653:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
 654:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 655:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
 656:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
 657:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
 658:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 659:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
 660:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
 661:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 662:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
 663:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
 664:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 665:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
 666:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
 667:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
 668:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 669:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
 670:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
 671:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 672:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
 673:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
 674:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 675:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
 676:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
 677:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
 678:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 679:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
 680:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
 681:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 682:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
 683:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
 684:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 685:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
 686:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
 687:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 688:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
 689:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
 690:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 691:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SCB */
 692:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 693:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 694:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 695:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 696:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
 697:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
 698:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 699:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 700:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 701:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 702:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
 703:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 704:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 705:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 706:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
 707:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
 708:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 709:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } SCnSCB_Type;
 710:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 711:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Interrupt Controller Type Register Definitions */
 712:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
 713:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
 714:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 715:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Auxiliary Control Register Definitions */
 716:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: 
 717:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: 
 718:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 719:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: 
 720:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: 
 721:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 722:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
 723:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
 724:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 725:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
 726:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
 727:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 728:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
 729:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
 730:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 731:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
 732:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 733:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 734:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 735:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 736:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 737:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Timer Registers.
 738:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 739:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 740:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 741:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 742:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Timer (SysTick).
 743:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 744:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 745:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 746:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 747:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 748:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 749:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 750:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } SysTick_Type;
 751:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 752:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Control / Status Register Definitions */
 753:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 754:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 755:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 756:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 757:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 758:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 759:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 760:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 761:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 762:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 763:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 764:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 765:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Reload Register Definitions */
 766:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 767:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 768:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 769:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Current Register Definitions */
 770:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 771:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 772:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 773:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Calibration Register Definitions */
 774:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 775:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 776:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 777:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 778:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 779:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 780:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 781:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 782:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 783:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SysTick */
 784:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 785:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 786:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 787:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 788:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
 789:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
 790:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 791:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 792:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 793:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 794:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 795:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 796:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 797:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 798:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  union
 799:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 800:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
 801:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
 802:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
 803:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
 804:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[864U];
 805:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
 806:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[15U];
 807:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
 808:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[15U];
 809:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
 810:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[29U];
 811:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
 812:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
 813:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
 814:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[43U];
 815:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
 816:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
 817:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[6U];
 818:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
 819:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
 820:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
 821:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
 822:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
 823:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
 824:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
 825:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
 826:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
 827:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
 828:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
 829:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
 830:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } ITM_Type;
 831:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 832:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Trace Privilege Register Definitions */
 833:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
 834:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM 
 835:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 836:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Trace Control Register Definitions */
 837:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
 838:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
 839:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 840:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
 841:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
 842:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 843:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
 844:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
 845:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 846:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
 847:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
 848:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 849:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
 850:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
 851:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 852:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
 853:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
 854:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 855:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
 856:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
 857:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 858:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
 859:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
 860:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 861:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
 862:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
 863:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 864:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Write Register Definitions */
 865:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
 866:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
 867:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 868:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Read Register Definitions */
 869:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
 870:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
 871:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 872:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Mode Control Register Definitions */
 873:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
 874:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
 875:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 876:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Lock Status Register Definitions */
 877:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
 878:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
 879:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 880:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
 881:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
 882:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 883:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
 884:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
 885:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 886:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
 887:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 888:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 889:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 890:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 891:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
 892:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
 893:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 894:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 895:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 896:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 897:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 898:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 899:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 900:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
 901:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
 902:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
 903:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
 904:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
 905:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
 906:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
 907:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
 908:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
 909:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
 910:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
 911:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
 912:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
 913:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
 914:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
 915:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
 916:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[1U];
 917:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
 918:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
 919:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
 920:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[1U];
 921:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
 922:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
 923:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 924:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } DWT_Type;
 925:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 926:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Control Register Definitions */
 927:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
 928:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
 929:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 930:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
 931:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
 932:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 933:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
 934:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
 935:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 936:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
 937:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
 938:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 939:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
 940:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
 941:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 942:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
 943:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
 944:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 945:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
 946:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
 947:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 948:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
 949:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
 950:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 951:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
 952:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
 953:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 954:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
 955:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
 956:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 957:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
 958:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
 959:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 960:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
 961:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
 962:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 963:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
 964:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
 965:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 966:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
 967:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
 968:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 969:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
 970:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
 971:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 972:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
 973:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
 974:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 975:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
 976:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
 977:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 978:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
 979:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
 980:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 981:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT CPI Count Register Definitions */
 982:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
 983:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
 984:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 985:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
 986:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
 987:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
 988:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 989:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Sleep Count Register Definitions */
 990:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
 991:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
 992:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 993:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT LSU Count Register Definitions */
 994:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
 995:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
 996:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
 997:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
 998:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
 999:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
1000:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1001:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Comparator Mask Register Definitions */
1002:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
1003:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
1004:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1005:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Comparator Function Register Definitions */
1006:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
1007:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
1008:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1009:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
1010:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
1011:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1012:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
1013:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
1014:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1015:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
1016:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
1017:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1018:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
1019:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
1020:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1021:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
1022:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
1023:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1024:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
1025:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
1026:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1027:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
1028:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
1029:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1030:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
1031:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
1032:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1033:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
1034:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1035:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1036:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1037:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1038:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
1039:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
1040:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1041:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1042:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1043:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1044:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
1045:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1046:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1047:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1048:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
1049:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
1050:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[2U];
1051:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
1052:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[55U];
1053:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
1054:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[131U];
1055:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
1056:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
1057:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
1058:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[759U];
1059:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
1060:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
1061:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
1062:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[1U];
1063:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
1064:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
1065:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
1066:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[39U];
1067:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
1068:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
1069:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED7[8U];
1070:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
1071:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
1072:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } TPI_Type;
1073:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1074:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
1075:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
1076:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
1077:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1078:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
1079:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
1080:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
1081:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1082:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
1083:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
1084:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
1085:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1086:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
1087:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
1088:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1089:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
1090:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
1091:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1092:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
1093:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
1094:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1095:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
1096:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
1097:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
1098:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1099:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
1100:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
1101:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1102:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI TRIGGER Register Definitions */
1103:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
1104:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
1105:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1106:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
1107:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1108:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
1109:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1110:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1111:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
1112:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1113:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1114:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
1115:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1116:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1117:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
1118:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1119:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
1120:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
1121:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1122:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
1123:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
1124:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1125:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
1126:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
1127:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1128:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
1129:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITA
1130:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITA
1131:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1132:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
1133:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1134:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
1135:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1136:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1137:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
1138:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1139:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1140:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
1141:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1142:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1143:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
1144:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1145:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
1146:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
1147:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1148:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
1149:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
1150:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1151:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
1152:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
1153:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1154:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
1155:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITA
1156:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITA
1157:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1158:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
1159:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
1160:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
1161:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1162:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI DEVID Register Definitions */
1163:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
1164:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
1165:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1166:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
1167:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
1168:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1169:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
1170:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
1171:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1172:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
1173:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
1174:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1175:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
1176:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
1177:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1178:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
1179:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
1180:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1181:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI DEVTYPE Register Definitions */
1182:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEV
1183:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
1184:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1185:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEV
1186:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
1187:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1188:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
1189:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1190:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1191:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__MPU_PRESENT == 1U)
1192:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1193:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1194:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
1195:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
1196:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1197:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1198:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1199:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1200:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
1201:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1202:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1203:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1204:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
1205:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
1206:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
1207:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
1208:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
1209:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
1210:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
1211:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
1212:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
1213:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
1214:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
1215:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } MPU_Type;
1216:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1217:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Type Register Definitions */
1218:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
1219:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
1220:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1221:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
1222:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
1223:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1224:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
1225:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
1226:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1227:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Control Register Definitions */
1228:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
1229:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
1230:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1231:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
1232:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
1233:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1234:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
1235:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
1236:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1237:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Number Register Definitions */
1238:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
1239:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
1240:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1241:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Base Address Register Definitions */
1242:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
1243:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
1244:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1245:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
1246:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
1247:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1248:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
1249:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
1250:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1251:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
1252:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
1253:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
1254:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1255:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
1256:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
1257:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1258:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
1259:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
1260:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1261:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
1262:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
1263:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1264:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
1265:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
1266:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1267:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
1268:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
1269:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1270:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
1271:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
1272:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1273:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
1274:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
1275:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1276:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
1277:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
1278:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1279:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
1280:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
1281:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1282:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_MPU */
1283:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1284:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1285:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1286:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__FPU_PRESENT == 1U)
1287:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1288:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1289:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
1290:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
1291:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1292:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1293:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1294:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1295:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
1296:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1297:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1298:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1299:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
1300:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
1301:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
1302:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
1303:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
1304:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
1305:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } FPU_Type;
1306:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1307:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Context Control Register Definitions */
1308:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
1309:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
1310:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1311:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
1312:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
1313:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1314:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
1315:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
1316:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1317:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
1318:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
1319:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1320:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
1321:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
1322:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1323:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
1324:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
1325:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1326:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
1327:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
1328:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1329:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
1330:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
1331:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1332:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
1333:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
1334:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1335:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Context Address Register Definitions */
1336:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
1337:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
1338:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1339:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
1340:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
1341:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
1342:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1343:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
1344:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
1345:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1346:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
1347:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
1348:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1349:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
1350:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
1351:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1352:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
1353:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
1354:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
1355:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1356:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
1357:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
1358:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1359:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
1360:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
1361:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1362:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
1363:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
1364:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1365:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
1366:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
1367:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1368:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
1369:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
1370:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1371:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
1372:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
1373:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1374:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
1375:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
1376:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1377:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
1378:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
1379:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
1380:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1381:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
1382:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
1383:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1384:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
1385:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
1386:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1387:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
1388:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
1389:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1390:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_FPU */
1391:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1392:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1393:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1394:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1395:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1396:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
1397:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Core Debug Registers
1398:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1399:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1400:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1401:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1402:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
1403:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1404:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1405:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1406:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
1407:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
1408:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
1409:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
1410:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** } CoreDebug_Type;
1411:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1412:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
1413:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
1414:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
1415:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1416:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
1417:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
1418:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1419:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
1420:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
1421:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1422:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
1423:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
1424:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1425:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
1426:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
1427:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1428:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
1429:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
1430:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1431:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
1432:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
1433:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1434:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
1435:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
1436:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1437:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
1438:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
1439:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1440:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
1441:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
1442:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1443:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
1444:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
1445:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1446:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
1447:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
1448:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1449:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Core Register Selector Register Definitions */
1450:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
1451:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
1452:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1453:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
1454:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
1455:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1456:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
1457:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
1458:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
1459:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1460:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
1461:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
1462:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1463:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
1464:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
1465:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1466:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
1467:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
1468:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1469:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
1470:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
1471:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1472:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
1473:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
1474:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1475:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
1476:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
1477:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1478:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
1479:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
1480:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1481:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
1482:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
1483:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1484:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
1485:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
1486:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1487:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
1488:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
1489:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1490:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
1491:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
1492:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1493:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
1494:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
1495:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1496:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
1497:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1498:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1499:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1500:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
1501:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
1502:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1503:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1504:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1505:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1506:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1507:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
1508:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] field  Name of the register bit field.
1509:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] value  Value of the bit field.
1510:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \return           Masked and shifted value.
1511:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** */
1512:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
1513:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1514:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1515:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief     Mask and shift a register value to extract a bit filed value.
1516:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] field  Name of the register bit field.
1517:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] value  Value of register.
1518:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \return           Masked and shifted bit field value.
1519:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** */
1520:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
1521:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1522:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
1523:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1524:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1525:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1526:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
1527:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_core_base     Core Definitions
1528:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Definitions for base addresses, unions, and structures.
1529:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1530:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1531:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1532:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* Memory mapping of Cortex-M4 Hardware */
1533:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
1534:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
1535:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
1536:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
1537:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
1538:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
1539:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
1540:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
1541:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1542:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
1543:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
1544:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
1545:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
1546:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
1547:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
1548:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
1549:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
1550:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1551:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__MPU_PRESENT == 1U)
1552:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
1553:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
1554:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1555:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1556:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__FPU_PRESENT == 1U)
1557:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
1558:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
1559:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1560:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1561:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} */
1562:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1563:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1564:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1565:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
1566:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  *                Hardware Abstraction Layer
1567:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   Core Function Interface contains:
1568:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core NVIC Functions
1569:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SysTick Functions
1570:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Debug Functions
1571:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Register Access Functions
1572:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
1573:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1574:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1575:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** */
1576:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1577:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1578:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1579:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /* ##########################   NVIC functions  #################################### */
1580:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1581:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
1582:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1583:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
1584:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1585:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1586:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1587:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1588:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Set Priority Grouping
1589:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Sets the priority grouping field using the required unlock sequence.
1590:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1591:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****            Only values from 0..7 are used.
1592:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****            In case of a conflict between priority grouping and available
1593:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1594:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      PriorityGroup  Priority grouping field.
1595:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1596:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1597:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1598:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t reg_value;
1599:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
1600:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1601:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
1602:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
1603:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value  =  (reg_value                                   |
1604:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1605:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****                 (PriorityGroupTmp << 8U)                      );              /* Insert write key a
1606:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   SCB->AIRCR =  reg_value;
1607:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1608:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1609:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1610:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1611:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Get Priority Grouping
1612:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
1613:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1614:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1615:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1616:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1617:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1618:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1619:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1620:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1621:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1622:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Enable External Interrupt
1623:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Enables a device-specific interrupt in the NVIC interrupt controller.
1624:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
1625:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1626:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1627:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1628:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1629:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1630:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1631:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1632:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1633:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Disable External Interrupt
1634:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Disables a device-specific interrupt in the NVIC interrupt controller.
1635:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
1636:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1637:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1638:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1639:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1640:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1641:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1642:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1643:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1644:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Get Pending Interrupt
1645:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Reads the pending register in the NVIC and returns the pending bit for the specified int
1646:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  Interrupt number.
1647:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \return             0  Interrupt status is not pending.
1648:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \return             1  Interrupt status is pending.
1649:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1650:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1651:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1652:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
1653:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1654:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1655:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1656:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1657:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Set Pending Interrupt
1658:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Sets the pending bit of an external interrupt.
1659:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  Interrupt number. Value cannot be negative.
1660:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1661:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1662:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1663:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1664:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1665:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1666:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1667:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1668:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Clear Pending Interrupt
1669:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Clears the pending bit of an external interrupt.
1670:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
1671:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1672:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1673:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1674:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1675:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1676:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1677:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1678:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1679:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Get Active Interrupt
1680:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Reads the active register in NVIC and returns the active bit.
1681:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  Interrupt number.
1682:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \return             0  Interrupt status is not active.
1683:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \return             1  Interrupt status is active.
1684:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1685:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1686:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
1687:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
1688:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
1689:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1690:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** 
1691:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1692:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Set Interrupt Priority
1693:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Sets the priority of an interrupt.
1694:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \note    The priority cannot be set for every core interrupt.
1695:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  Interrupt number.
1696:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]  priority  Priority to set.
1697:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1698:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1699:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** {
  26              		.loc 1 1699 0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 8
  29              		@ frame_needed = 1, uses_anonymous_args = 0
  30              		@ link register save eliminated.
  31 0000 80B4     		push	{r7}
  32              		.cfi_def_cfa_offset 4
  33              		.cfi_offset 7, -4
  34 0002 83B0     		sub	sp, sp, #12
  35              		.cfi_def_cfa_offset 16
  36 0004 00AF     		add	r7, sp, #0
  37              		.cfi_def_cfa_register 7
  38 0006 0346     		mov	r3, r0
  39 0008 3960     		str	r1, [r7]
  40 000a FB71     		strb	r3, [r7, #7]
1700:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   if ((int32_t)(IRQn) < 0)
  41              		.loc 1 1700 0
  42 000c 97F90730 		ldrsb	r3, [r7, #7]
  43 0010 002B     		cmp	r3, #0
  44 0012 0BDA     		bge	.L2
1701:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   {
1702:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
  45              		.loc 1 1702 0
  46 0014 3B68     		ldr	r3, [r7]
  47 0016 DAB2     		uxtb	r2, r3
  48 0018 0C49     		ldr	r1, .L5
  49 001a FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
  50 001c 03F00F03 		and	r3, r3, #15
  51 0020 043B     		subs	r3, r3, #4
  52 0022 5201     		lsls	r2, r2, #5
  53 0024 D2B2     		uxtb	r2, r2
  54 0026 0B44     		add	r3, r3, r1
  55 0028 1A76     		strb	r2, [r3, #24]
1703:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   }
1704:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   else
1705:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   {
1706:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****     NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
1707:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   }
1708:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h **** }
  56              		.loc 1 1708 0
  57 002a 09E0     		b	.L4
  58              	.L2:
1706:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH07-TIMER\Systick(MSP432)-20210406\02_CPU\core_cm4.h ****   }
  59              		.loc 1 1706 0
  60 002c 3B68     		ldr	r3, [r7]
  61 002e DAB2     		uxtb	r2, r3
  62 0030 0749     		ldr	r1, .L5+4
  63 0032 97F90730 		ldrsb	r3, [r7, #7]
  64 0036 5201     		lsls	r2, r2, #5
  65 0038 D2B2     		uxtb	r2, r2
  66 003a 0B44     		add	r3, r3, r1
  67 003c 83F80023 		strb	r2, [r3, #768]
  68              	.L4:
  69              		.loc 1 1708 0
  70 0040 00BF     		nop
  71 0042 0C37     		adds	r7, r7, #12
  72              		.cfi_def_cfa_offset 4
  73 0044 BD46     		mov	sp, r7
  74              		.cfi_def_cfa_register 13
  75              		@ sp needed
  76 0046 5DF8047B 		ldr	r7, [sp], #4
  77              		.cfi_restore 7
  78              		.cfi_def_cfa_offset 0
  79 004a 7047     		bx	lr
  80              	.L6:
  81              		.align	2
  82              	.L5:
  83 004c 00ED00E0 		.word	-536810240
  84 0050 00E100E0 		.word	-536813312
  85              		.cfi_endproc
  86              	.LFE114:
  88              		.align	1
  89              		.global	systick_init
  90              		.syntax unified
  91              		.thumb
  92              		.thumb_func
  93              		.fpu fpv4-sp-d16
  95              	systick_init:
  96              	.LFB123:
  97              		.file 2 "srcc/systick.c"
   1:srcc/systick.c **** //==========================================================================
   2:srcc/systick.c **** //ÎÄ¼þÃû³Æ£ºsystick.c
   3:srcc/systick.c **** //¹¦ÄÜ¸ÅÒª£ºsystick ¹¹¼þÔ´ÎÄ¼þ
   4:srcc/systick.c **** //°æÈ¨ËùÓÐ£ºËÕÖÝ´óÑ§Ç¶ÈëÊ½ÖÐÐÄ(sumcu.suda.edu.cn)
   5:srcc/systick.c **** //¸üÐÂ¼ÇÂ¼£º2017-11-08   V1.0
   6:srcc/systick.c **** //==========================================================================
   7:srcc/systick.c **** 
   8:srcc/systick.c **** #include "systick.h"
   9:srcc/systick.c **** 
  10:srcc/systick.c **** //===========================================================================
  11:srcc/systick.c **** //º¯ÊýÃû³Æ£ºsystick_init
  12:srcc/systick.c **** //º¯Êý·µ»Ø£ºÎÞ
  13:srcc/systick.c **** //²ÎÊýËµÃ÷£ºint_ms:ÖÐ¶ÏµÄÊ±¼ä¼ä¸ô¡£µ¥Î»ms ÍÆ¼öÑ¡ÓÃ5,10,......
  14:srcc/systick.c **** //¹¦ÄÜ¸ÅÒª£º³õÊ¼»¯SysTickÄ£¿é£¬ÉèÖÃÖÐ¶ÏµÄÊ±¼ä¼ä¸ô
  15:srcc/systick.c **** //Ëµ    Ã÷£ºÄÚºËÊ±ÖÓÆµÂÊSYSTEM_CLK_KHZºê¶¨ÒåÔÚcommon.hÖÐ
  16:srcc/systick.c **** //systickÒÔmsÎªµ¥Î»£¬×î´ó¿ÉÎª5592£¨2^24/3000£¬ÏòÏÂÈ¡Õû£©£¬ºÏÀí·¶Î§1~5592¡£
  17:srcc/systick.c **** //MSP432P401R µÄSysTickÊ±ÖÓÔ´Ö»ÄÜÊÇÄÚºËÊ±ÖÓ
  18:srcc/systick.c **** //24Î»¼ÆÊýÆ÷£¬¼õ1¼ÆÊý
  19:srcc/systick.c **** //Ê±¼ä·¶Î§£º1ms~5592ms£¨ÄÚºËÊ±ÖÓ£©
  20:srcc/systick.c **** //===========================================================================
  21:srcc/systick.c **** void systick_init( uint8_t int_ms)
  22:srcc/systick.c **** {
  98              		.loc 2 22 0
  99              		.cfi_startproc
 100              		@ args = 0, pretend = 0, frame = 8
 101              		@ frame_needed = 1, uses_anonymous_args = 0
 102 0054 80B5     		push	{r7, lr}
 103              		.cfi_def_cfa_offset 8
 104              		.cfi_offset 7, -8
 105              		.cfi_offset 14, -4
 106 0056 82B0     		sub	sp, sp, #8
 107              		.cfi_def_cfa_offset 16
 108 0058 00AF     		add	r7, sp, #0
 109              		.cfi_def_cfa_register 7
 110 005a 0346     		mov	r3, r0
 111 005c FB71     		strb	r3, [r7, #7]
  23:srcc/systick.c ****     SysTick->CTRL = 0;   //ÉèÖÃÇ°ÏÈ¹Ø±Õsystick¡£CTRL¿ØÖÆ¼°×´Ì¬¼Ä´æÆ÷
 112              		.loc 2 23 0
 113 005e 0F4B     		ldr	r3, .L9
 114 0060 0022     		movs	r2, #0
 115 0062 1A60     		str	r2, [r3]
  24:srcc/systick.c ****     SysTick->VAL  = 0;   //Çå³ý¼ÆÊýÆ÷¡£VAL ¼ÆÊýÆ÷
 116              		.loc 2 24 0
 117 0064 0D4B     		ldr	r3, .L9
 118 0066 0022     		movs	r2, #0
 119 0068 9A60     		str	r2, [r3, #8]
  25:srcc/systick.c ****     if((int_ms<1)||(int_ms>5592))
 120              		.loc 2 25 0
 121 006a FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 122 006c 002B     		cmp	r3, #0
 123 006e 01D1     		bne	.L8
  26:srcc/systick.c ****     {
  27:srcc/systick.c ****        int_ms = 10;
 124              		.loc 2 27 0
 125 0070 0A23     		movs	r3, #10
 126 0072 FB71     		strb	r3, [r7, #7]
 127              	.L8:
  28:srcc/systick.c ****     }
  29:srcc/systick.c ****     SysTick->LOAD = MCU_SYSTEM_CLK_KHZ*int_ms - 1UL;
 128              		.loc 2 29 0
 129 0074 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 130 0076 4BF68032 		movw	r2, #48000
 131 007a 02FB03F3 		mul	r3, r2, r3
 132 007e 074A     		ldr	r2, .L9
 133 0080 013B     		subs	r3, r3, #1
 134 0082 5360     		str	r3, [r2, #4]
  30:srcc/systick.c ****     //Éè¶¨ SysTickÓÅÏÈ¼¶Îª3(SHPR3¼Ä´æÆ÷µÄ×î¸ß×Ö½Ú=0xC0)
  31:srcc/systick.c ****     NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);
 135              		.loc 2 31 0
 136 0084 0721     		movs	r1, #7
 137 0086 4FF0FF30 		mov	r0, #-1
 138 008a FFF7B9FF 		bl	NVIC_SetPriority
  32:srcc/systick.c ****     //ÉèÖÃÊ±ÖÓÔ´,ÔÊÐíÖÐ¶Ï,Ê¹ÄÜ¸ÃÄ£¿é,¿ªÊ¼¼ÆÊý
  33:srcc/systick.c ****     SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 139              		.loc 2 33 0
 140 008e 034B     		ldr	r3, .L9
 141 0090 0722     		movs	r2, #7
 142 0092 1A60     		str	r2, [r3]
  34:srcc/systick.c ****                      SysTick_CTRL_TICKINT_Msk   |
  35:srcc/systick.c ****                      SysTick_CTRL_ENABLE_Msk;
  36:srcc/systick.c **** 
  37:srcc/systick.c **** }
 143              		.loc 2 37 0
 144 0094 00BF     		nop
 145 0096 0837     		adds	r7, r7, #8
 146              		.cfi_def_cfa_offset 8
 147 0098 BD46     		mov	sp, r7
 148              		.cfi_def_cfa_register 13
 149              		@ sp needed
 150 009a 80BD     		pop	{r7, pc}
 151              	.L10:
 152              		.align	2
 153              	.L9:
 154 009c 10E000E0 		.word	-536813552
 155              		.cfi_endproc
 156              	.LFE123:
 158              	.Letext0:
 159              		.file 3 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 160              		.file 4 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 161              		.file 5 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH07-TIMER\
 162              		.file 6 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH07-TIMER\
DEFINED SYMBOLS
                            *ABS*:00000000 systick.c
C:\Users\lenovo\AppData\Local\Temp\ccLJieal.s:17     .text:00000000 $t
C:\Users\lenovo\AppData\Local\Temp\ccLJieal.s:23     .text:00000000 NVIC_SetPriority
C:\Users\lenovo\AppData\Local\Temp\ccLJieal.s:83     .text:0000004c $d
C:\Users\lenovo\AppData\Local\Temp\ccLJieal.s:88     .text:00000054 $t
C:\Users\lenovo\AppData\Local\Temp\ccLJieal.s:95     .text:00000054 systick_init
C:\Users\lenovo\AppData\Local\Temp\ccLJieal.s:154    .text:0000009c $d

NO UNDEFINED SYMBOLS
