   1              		.cpu cortex-m4
   2              		.eabi_attribute 27, 1
   3              		.eabi_attribute 28, 1
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 6
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.file	"uart.c"
  14              		.text
  15              	.Ltext0:
  16              		.cfi_sections	.debug_frame
  17              		.align	1
  18              		.syntax unified
  19              		.thumb
  20              		.thumb_func
  21              		.fpu fpv4-sp-d16
  23              	NVIC_EnableIRQ:
  24              	.LFB108:
  25              		.file 1 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH04-GPIO\\
   1:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**************************************************************************//**
   2:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @file     core_cm4.h
   3:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
   4:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @version  V4.30
   5:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  * @date     20. October 2015
   6:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
   7:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
   8:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
   9:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    All rights reserved.
  10:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    Redistribution and use in source and binary forms, with or without
  11:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    modification, are permitted provided that the following conditions are met:
  12:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    - Redistributions of source code must retain the above copyright
  13:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      notice, this list of conditions and the following disclaimer.
  14:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    - Redistributions in binary form must reproduce the above copyright
  15:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      notice, this list of conditions and the following disclaimer in the
  16:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      documentation and/or other materials provided with the distribution.
  17:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    - Neither the name of ARM nor the names of its contributors may be used
  18:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      to endorse or promote products derived from this software without
  19:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      specific prior written permission.
  20:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    *
  21:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  25:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    POSSIBILITY OF SUCH DAMAGE.
  32:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    ---------------------------------------------------------------------------*/
  33:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  34:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  35:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if   defined ( __ICCARM__ )
  36:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  #pragma system_include         /* treat file as system include file for MISRA check */
  37:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  38:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #pragma clang system_header   /* treat file as system include file */
  39:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
  40:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  41:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
  42:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORE_CM4_H_GENERIC
  43:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  44:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include <stdint.h>
  45:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  46:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
  47:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  extern "C" {
  48:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
  49:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  50:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
  51:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  52:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   CMSIS violates the following MISRA-C:2004 rules:
  53:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  54:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  55:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      Function definitions in header files are used to allow 'inlining'.
  56:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  57:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  58:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      Unions are used for effective representation of core registers.
  59:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  60:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  61:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****      Function-like macros are used to allow more efficient code.
  62:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
  63:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  64:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  65:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
  66:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  *                 CMSIS definitions
  67:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
  68:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
  69:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup Cortex_M4
  70:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
  71:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
  72:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  73:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*  CMSIS CM4 definitions */
  74:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS H
  75:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS H
  76:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
  77:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****                                     __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL versi
  78:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  79:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core *
  80:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  81:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  82:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if   defined ( __CC_ARM )
  83:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
  84:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
  85:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static __inline
  86:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  87:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  88:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
  89:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
  90:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static __inline
  91:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  92:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __GNUC__ )
  93:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for GNU Comp
  94:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for GNU C
  95:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
  96:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
  97:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __ICCARM__ )
  98:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for IAR Comp
  99:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for IAR C
 100:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 101:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 102:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TMS470__ )
 103:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TI CCS C
 104:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 105:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 106:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TASKING__ )
 107:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TASKING 
 108:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for TASKI
 109:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 110:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 111:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __CSMC__ )
 112:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __packed
 113:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Co
 114:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __INLINE         inline                                    /*!< inline keyword for COSMIC
 115:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define __STATIC_INLINE  static inline
 116:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 117:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #else
 118:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #error Unknown compiler
 119:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 120:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 121:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
 122:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
 123:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
 124:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if defined ( __CC_ARM )
 125:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __TARGET_FPU_VFP
 126:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 127:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 128:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 129:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 130:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 131:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 132:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 133:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 134:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 135:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 136:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
 137:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __ARM_PCS_VFP
 138:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1)
 139:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 140:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 141:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
 142:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 143:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 144:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 145:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 146:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 147:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 148:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __GNUC__ )
 149:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
 150:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 151:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 152:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 153:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 154:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 155:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 156:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 157:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 158:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 159:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 160:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __ICCARM__ )
 161:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __ARMVFP__
 162:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 163:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 164:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 165:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 166:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 167:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 168:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 169:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 170:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 171:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 172:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TMS470__ )
 173:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __TI_VFP_SUPPORT__
 174:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 175:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 176:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 177:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 178:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 179:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 180:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 181:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 182:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 183:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 184:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __TASKING__ )
 185:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if defined __FPU_VFP__
 186:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 187:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 188:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 189:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 190:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 191:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 192:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 193:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 194:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 195:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 196:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #elif defined ( __CSMC__ )
 197:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #if ( __CSMC__ & 0x400U)
 198:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #if (__FPU_PRESENT == 1U)
 199:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       1U
 200:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #else
 201:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
 202:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****       #define __FPU_USED       0U
 203:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #endif
 204:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #else
 205:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_USED         0U
 206:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 207:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 208:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 209:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 210:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmInstr.h"                /* Core Instruction Access */
 211:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmFunc.h"                 /* Core Function Access */
 212:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
 213:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 214:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 215:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
 216:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 217:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 218:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
 219:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 220:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CMSIS_GENERIC
 221:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 222:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
 223:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
 224:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 225:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 226:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  extern "C" {
 227:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 228:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 229:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* check device defines and use defaults */
 230:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
 231:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __CM4_REV
 232:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __CM4_REV               0x0000U
 233:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__CM4_REV not defined in device header file; using default!"
 234:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 235:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 236:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __FPU_PRESENT
 237:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __FPU_PRESENT             0U
 238:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
 239:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 240:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 241:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __MPU_PRESENT
 242:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __MPU_PRESENT             0U
 243:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
 244:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 245:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 246:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __NVIC_PRIO_BITS
 247:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __NVIC_PRIO_BITS          4U
 248:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 249:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 250:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 251:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #ifndef __Vendor_SysTickConfig
 252:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #define __Vendor_SysTickConfig    0U
 253:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 254:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #endif
 255:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 256:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 257:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
 258:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 259:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 260:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 261:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     <strong>IO Type Qualifiers</strong> are used
 262:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     \li to specify the access to peripheral variables.
 263:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     \li for automatic generation of peripheral register debug information.
 264:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
 265:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #ifdef __cplusplus
 266:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 267:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #else
 268:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 269:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
 270:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 271:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 272:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 273:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* following defines should be used for structure members */
 274:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 275:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 276:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 277:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 278:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group Cortex_M4 */
 279:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 280:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 281:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 282:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
 283:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  *                 Register Abstraction
 284:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   Core Register contain:
 285:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Register
 286:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core NVIC Register
 287:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SCB Register
 288:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SysTick Register
 289:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Debug Register
 290:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core MPU Register
 291:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core FPU Register
 292:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
 293:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 294:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 295:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 296:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
 297:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 298:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 299:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
 300:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 301:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Core Register type definitions.
 302:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 303:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 304:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 305:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 306:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 307:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 308:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 309:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 310:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 311:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 312:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
 313:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 314:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
 315:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 316:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 317:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 318:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 319:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 320:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 321:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 322:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } APSR_Type;
 323:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 324:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* APSR Register Definitions */
 325:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 326:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 327:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 328:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 329:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 330:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 331:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 332:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 333:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 334:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 335:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 336:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 337:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
 338:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
 339:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 340:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
 341:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
 342:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 343:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 344:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 345:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 346:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 347:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 348:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 349:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 350:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 351:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 352:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 353:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 354:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 355:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } IPSR_Type;
 356:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 357:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* IPSR Register Definitions */
 358:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 359:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 360:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 361:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 362:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 363:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 364:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 365:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 366:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 367:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 368:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 369:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 370:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
 371:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
 372:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
 373:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 374:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
 375:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
 376:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 377:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 378:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 379:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 380:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 381:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 382:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } xPSR_Type;
 383:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 384:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* xPSR Register Definitions */
 385:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 386:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 387:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 388:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 389:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 390:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 391:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 392:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 393:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 394:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 395:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 396:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 397:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
 398:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
 399:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 400:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_IT_Pos                        25U                                            /*!< xPSR
 401:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR
 402:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 403:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 404:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 405:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 406:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
 407:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
 408:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 409:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 410:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 411:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 412:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 413:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 414:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Union type to access the Control Registers (CONTROL).
 415:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 416:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef union
 417:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 418:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   struct
 419:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 420:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
 421:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 422:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
 423:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
 424:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
 425:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
 426:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } CONTROL_Type;
 427:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 428:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* CONTROL Register Definitions */
 429:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
 430:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
 431:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 432:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 433:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 434:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 435:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
 436:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
 437:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 438:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_CORE */
 439:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 440:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 441:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 442:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
 443:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 444:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Type definitions for the NVIC Registers
 445:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 446:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 447:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 448:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 449:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 450:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 451:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 452:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 453:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 454:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[24U];
 455:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 456:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RSERVED1[24U];
 457:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 458:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[24U];
 459:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 460:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[24U];
 461:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
 462:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[56U];
 463:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
 464:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[644U];
 465:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
 466:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }  NVIC_Type;
 467:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 468:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
 469:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
 470:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
 471:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 472:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_NVIC */
 473:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 474:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 475:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 476:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 477:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 478:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Control Block Registers
 479:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 480:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 481:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 482:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 483:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Control Block (SCB).
 484:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 485:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 486:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 487:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 488:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 489:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 490:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 491:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 492:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 493:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
 494:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 495:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
 496:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
 497:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
 498:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
 499:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
 500:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
 501:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
 502:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
 503:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
 504:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
 505:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
 506:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[5U];
 507:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
 508:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } SCB_Type;
 509:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 510:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB CPUID Register Definitions */
 511:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 512:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 513:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 514:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 515:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 516:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 517:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 518:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 519:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 520:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 521:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 522:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 523:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 524:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 525:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 526:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
 527:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 528:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 529:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 530:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 531:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 532:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 533:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 534:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 535:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 536:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 537:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 538:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 539:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 540:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 541:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 542:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 543:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 544:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 545:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 546:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 547:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 548:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 549:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 550:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 551:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
 552:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
 553:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 554:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 555:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 556:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 557:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
 558:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
 559:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
 560:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 561:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 562:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 563:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 564:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 565:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 566:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 567:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 568:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 569:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 570:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 571:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
 572:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
 573:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 574:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 575:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 576:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 577:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 578:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 579:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 580:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
 581:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
 582:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 583:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB System Control Register Definitions */
 584:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 585:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 586:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 587:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 588:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 589:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 590:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 591:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 592:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 593:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Configuration Control Register Definitions */
 594:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 595:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 596:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 597:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
 598:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
 599:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 600:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
 601:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
 602:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 603:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 604:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 605:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 606:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
 607:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
 608:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 609:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
 610:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
 611:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 612:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
 613:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
 614:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
 615:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 616:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
 617:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
 618:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 619:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
 620:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
 621:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 622:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 623:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 624:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 625:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
 626:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
 627:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 628:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
 629:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
 630:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 631:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
 632:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
 633:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 634:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
 635:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
 636:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 637:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
 638:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
 639:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 640:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
 641:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
 642:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 643:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
 644:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
 645:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 646:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
 647:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
 648:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 649:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
 650:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
 651:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 652:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
 653:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
 654:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 655:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
 656:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
 657:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
 658:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 659:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
 660:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
 661:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 662:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
 663:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
 664:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 665:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
 666:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
 667:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
 668:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 669:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
 670:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
 671:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 672:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
 673:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
 674:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 675:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
 676:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
 677:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
 678:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 679:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
 680:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
 681:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 682:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
 683:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
 684:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 685:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
 686:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
 687:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 688:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
 689:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
 690:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 691:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SCB */
 692:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 693:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 694:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 695:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 696:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
 697:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
 698:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 699:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 700:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 701:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 702:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
 703:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 704:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 705:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 706:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
 707:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
 708:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 709:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } SCnSCB_Type;
 710:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 711:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Interrupt Controller Type Register Definitions */
 712:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
 713:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
 714:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 715:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Auxiliary Control Register Definitions */
 716:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: 
 717:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: 
 718:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 719:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: 
 720:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: 
 721:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 722:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
 723:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
 724:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 725:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
 726:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
 727:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 728:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
 729:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
 730:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 731:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
 732:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 733:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 734:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 735:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 736:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 737:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the System Timer Registers.
 738:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 739:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 740:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 741:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 742:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the System Timer (SysTick).
 743:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 744:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 745:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 746:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 747:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 748:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 749:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 750:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } SysTick_Type;
 751:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 752:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Control / Status Register Definitions */
 753:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 754:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 755:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 756:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 757:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 758:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 759:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 760:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 761:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 762:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 763:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 764:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 765:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Reload Register Definitions */
 766:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 767:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 768:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 769:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Current Register Definitions */
 770:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 771:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 772:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 773:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* SysTick Calibration Register Definitions */
 774:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 775:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 776:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 777:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 778:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 779:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 780:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 781:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 782:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 783:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_SysTick */
 784:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 785:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 786:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 787:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 788:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
 789:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
 790:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 791:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 792:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 793:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 794:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 795:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 796:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 797:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 798:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  union
 799:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   {
 800:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
 801:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
 802:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
 803:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
 804:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[864U];
 805:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
 806:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[15U];
 807:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
 808:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[15U];
 809:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
 810:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[29U];
 811:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
 812:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
 813:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
 814:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[43U];
 815:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
 816:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
 817:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[6U];
 818:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
 819:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
 820:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
 821:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
 822:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
 823:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
 824:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
 825:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
 826:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
 827:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
 828:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
 829:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
 830:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } ITM_Type;
 831:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 832:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Trace Privilege Register Definitions */
 833:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
 834:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM 
 835:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 836:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Trace Control Register Definitions */
 837:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
 838:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
 839:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 840:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
 841:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
 842:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 843:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
 844:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
 845:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 846:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
 847:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
 848:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 849:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
 850:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
 851:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 852:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
 853:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
 854:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 855:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
 856:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
 857:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 858:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
 859:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
 860:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 861:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
 862:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
 863:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 864:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Write Register Definitions */
 865:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
 866:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
 867:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 868:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Read Register Definitions */
 869:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
 870:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
 871:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 872:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Integration Mode Control Register Definitions */
 873:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
 874:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
 875:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 876:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ITM Lock Status Register Definitions */
 877:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
 878:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
 879:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 880:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
 881:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
 882:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 883:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
 884:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
 885:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 886:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
 887:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 888:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 889:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 890:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
 891:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
 892:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
 893:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
 894:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 895:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 896:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
 897:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 898:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
 899:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
 900:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
 901:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
 902:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
 903:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
 904:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
 905:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
 906:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
 907:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
 908:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
 909:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
 910:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
 911:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
 912:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
 913:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
 914:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
 915:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
 916:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[1U];
 917:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
 918:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
 919:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
 920:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[1U];
 921:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
 922:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
 923:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 924:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } DWT_Type;
 925:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 926:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Control Register Definitions */
 927:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
 928:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
 929:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 930:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
 931:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
 932:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 933:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
 934:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
 935:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 936:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
 937:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
 938:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 939:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
 940:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
 941:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 942:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
 943:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
 944:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 945:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
 946:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
 947:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 948:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
 949:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
 950:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 951:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
 952:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
 953:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 954:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
 955:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
 956:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 957:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
 958:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
 959:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 960:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
 961:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
 962:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 963:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
 964:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
 965:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 966:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
 967:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
 968:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 969:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
 970:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
 971:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 972:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
 973:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
 974:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 975:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
 976:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
 977:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 978:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
 979:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
 980:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 981:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT CPI Count Register Definitions */
 982:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
 983:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
 984:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 985:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
 986:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
 987:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
 988:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 989:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Sleep Count Register Definitions */
 990:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
 991:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
 992:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 993:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT LSU Count Register Definitions */
 994:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
 995:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
 996:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
 997:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
 998:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
 999:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
1000:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1001:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Comparator Mask Register Definitions */
1002:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
1003:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
1004:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1005:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* DWT Comparator Function Register Definitions */
1006:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
1007:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
1008:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1009:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
1010:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
1011:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1012:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
1013:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
1014:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1015:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
1016:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
1017:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1018:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
1019:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
1020:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1021:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
1022:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
1023:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1024:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
1025:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
1026:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1027:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
1028:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
1029:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1030:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
1031:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
1032:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1033:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
1034:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1035:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1036:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1037:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1038:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
1039:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
1040:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1041:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1042:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1043:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1044:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
1045:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1046:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1047:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1048:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
1049:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
1050:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[2U];
1051:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
1052:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED1[55U];
1053:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
1054:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED2[131U];
1055:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
1056:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
1057:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
1058:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED3[759U];
1059:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
1060:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
1061:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
1062:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED4[1U];
1063:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
1064:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
1065:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
1066:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED5[39U];
1067:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
1068:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
1069:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED7[8U];
1070:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
1071:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
1072:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } TPI_Type;
1073:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1074:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
1075:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
1076:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
1077:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1078:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
1079:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
1080:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
1081:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1082:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
1083:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
1084:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
1085:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1086:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
1087:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
1088:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1089:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
1090:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
1091:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1092:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
1093:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
1094:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1095:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
1096:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
1097:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
1098:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1099:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
1100:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
1101:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1102:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI TRIGGER Register Definitions */
1103:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
1104:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
1105:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1106:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
1107:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1108:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
1109:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1110:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1111:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
1112:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1113:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1114:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
1115:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1116:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1117:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
1118:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1119:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
1120:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
1121:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1122:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
1123:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
1124:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1125:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
1126:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
1127:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1128:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
1129:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITA
1130:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITA
1131:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1132:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
1133:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
1134:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
1135:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1136:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
1137:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
1138:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1139:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
1140:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
1141:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1142:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
1143:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
1144:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1145:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
1146:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
1147:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1148:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
1149:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
1150:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1151:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
1152:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
1153:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1154:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
1155:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITA
1156:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITA
1157:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1158:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
1159:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
1160:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
1161:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1162:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI DEVID Register Definitions */
1163:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
1164:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
1165:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1166:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
1167:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
1168:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1169:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
1170:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
1171:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1172:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
1173:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
1174:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1175:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
1176:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
1177:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1178:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
1179:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
1180:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1181:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* TPI DEVTYPE Register Definitions */
1182:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEV
1183:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
1184:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1185:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEV
1186:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
1187:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1188:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
1189:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1190:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1191:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__MPU_PRESENT == 1U)
1192:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1193:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1194:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
1195:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
1196:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1197:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1198:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1199:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1200:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
1201:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1202:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1203:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1204:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
1205:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
1206:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
1207:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
1208:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
1209:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
1210:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
1211:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
1212:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
1213:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
1214:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
1215:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } MPU_Type;
1216:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1217:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Type Register Definitions */
1218:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
1219:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
1220:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1221:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
1222:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
1223:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1224:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
1225:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
1226:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1227:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Control Register Definitions */
1228:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
1229:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
1230:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1231:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
1232:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
1233:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1234:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
1235:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
1236:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1237:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Number Register Definitions */
1238:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
1239:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
1240:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1241:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Base Address Register Definitions */
1242:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
1243:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
1244:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1245:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
1246:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
1247:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1248:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
1249:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
1250:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1251:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
1252:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
1253:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
1254:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1255:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
1256:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
1257:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1258:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
1259:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
1260:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1261:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
1262:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
1263:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1264:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
1265:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
1266:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1267:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
1268:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
1269:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1270:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
1271:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
1272:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1273:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
1274:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
1275:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1276:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
1277:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
1278:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1279:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
1280:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
1281:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1282:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_MPU */
1283:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1284:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1285:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1286:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__FPU_PRESENT == 1U)
1287:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1288:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1289:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
1290:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
1291:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1292:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1293:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1294:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1295:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
1296:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1297:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1298:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1299:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****         uint32_t RESERVED0[1U];
1300:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
1301:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
1302:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
1303:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
1304:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
1305:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } FPU_Type;
1306:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1307:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Context Control Register Definitions */
1308:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
1309:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
1310:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1311:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
1312:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
1313:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1314:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
1315:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
1316:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1317:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
1318:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
1319:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1320:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
1321:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
1322:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1323:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
1324:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
1325:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1326:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
1327:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
1328:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1329:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
1330:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
1331:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1332:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
1333:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
1334:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1335:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Context Address Register Definitions */
1336:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
1337:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
1338:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1339:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
1340:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
1341:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
1342:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1343:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
1344:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
1345:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1346:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
1347:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
1348:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1349:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
1350:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
1351:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1352:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
1353:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
1354:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
1355:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1356:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
1357:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
1358:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1359:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
1360:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
1361:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1362:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
1363:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
1364:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1365:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
1366:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
1367:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1368:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
1369:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
1370:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1371:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
1372:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
1373:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1374:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
1375:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
1376:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1377:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
1378:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
1379:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
1380:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1381:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
1382:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
1383:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1384:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
1385:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
1386:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1387:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
1388:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
1389:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1390:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_FPU */
1391:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1392:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1393:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1394:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1395:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_core_register
1396:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
1397:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Type definitions for the Core Debug Registers
1398:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1399:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1400:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1401:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1402:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
1403:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1404:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** typedef struct
1405:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1406:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
1407:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
1408:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
1409:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
1410:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** } CoreDebug_Type;
1411:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1412:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
1413:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
1414:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
1415:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1416:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
1417:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
1418:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1419:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
1420:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
1421:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1422:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
1423:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
1424:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1425:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
1426:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
1427:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1428:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
1429:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
1430:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1431:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
1432:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
1433:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1434:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
1435:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
1436:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1437:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
1438:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
1439:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1440:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
1441:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
1442:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1443:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
1444:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
1445:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1446:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
1447:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
1448:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1449:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Core Register Selector Register Definitions */
1450:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
1451:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
1452:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1453:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
1454:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
1455:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1456:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
1457:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
1458:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
1459:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1460:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
1461:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
1462:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1463:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
1464:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
1465:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1466:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
1467:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
1468:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1469:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
1470:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
1471:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1472:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
1473:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
1474:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1475:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
1476:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
1477:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1478:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
1479:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
1480:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1481:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
1482:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
1483:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1484:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
1485:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
1486:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1487:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
1488:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
1489:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1490:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
1491:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
1492:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1493:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
1494:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
1495:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1496:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
1497:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1498:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1499:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1500:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
1501:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
1502:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1503:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1504:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1505:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1506:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1507:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
1508:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] field  Name of the register bit field.
1509:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] value  Value of the bit field.
1510:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \return           Masked and shifted value.
1511:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
1512:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
1513:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1514:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1515:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief     Mask and shift a register value to extract a bit filed value.
1516:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] field  Name of the register bit field.
1517:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param[in] value  Value of register.
1518:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \return           Masked and shifted bit field value.
1519:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
1520:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
1521:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1522:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
1523:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1524:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1525:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1526:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup    CMSIS_core_register
1527:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup   CMSIS_core_base     Core Definitions
1528:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief      Definitions for base addresses, unions, and structures.
1529:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1530:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1531:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1532:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* Memory mapping of Cortex-M4 Hardware */
1533:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
1534:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
1535:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
1536:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
1537:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
1538:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
1539:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
1540:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
1541:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1542:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
1543:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
1544:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
1545:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
1546:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
1547:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
1548:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
1549:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
1550:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1551:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__MPU_PRESENT == 1U)
1552:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
1553:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
1554:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1555:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1556:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #if (__FPU_PRESENT == 1U)
1557:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
1558:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
1559:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** #endif
1560:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1561:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*@} */
1562:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1563:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1564:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1565:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /*******************************************************************************
1566:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  *                Hardware Abstraction Layer
1567:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   Core Function Interface contains:
1568:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core NVIC Functions
1569:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core SysTick Functions
1570:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Debug Functions
1571:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   - Core Register Access Functions
1572:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  ******************************************************************************/
1573:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1574:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1575:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** */
1576:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1577:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1578:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1579:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /* ##########################   NVIC functions  #################################### */
1580:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1581:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
1582:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1583:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
1584:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   @{
1585:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1586:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1587:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1588:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Set Priority Grouping
1589:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Sets the priority grouping field using the required unlock sequence.
1590:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1591:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            Only values from 0..7 are used.
1592:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            In case of a conflict between priority grouping and available
1593:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1594:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      PriorityGroup  Priority grouping field.
1595:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1596:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1597:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1598:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t reg_value;
1599:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
1600:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1601:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
1602:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
1603:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   reg_value  =  (reg_value                                   |
1604:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1605:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****                 (PriorityGroupTmp << 8U)                      );              /* Insert write key a
1606:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   SCB->AIRCR =  reg_value;
1607:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
1608:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1609:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1610:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1611:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Get Priority Grouping
1612:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
1613:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1614:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1615:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1616:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
1617:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1618:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
1619:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1620:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1621:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1622:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Enable External Interrupt
1623:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Enables a device-specific interrupt in the NVIC interrupt controller.
1624:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
1625:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1626:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1627:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
  26              		.loc 1 1627 0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 8
  29              		@ frame_needed = 1, uses_anonymous_args = 0
  30              		@ link register save eliminated.
  31 0000 80B4     		push	{r7}
  32              		.cfi_def_cfa_offset 4
  33              		.cfi_offset 7, -4
  34 0002 83B0     		sub	sp, sp, #12
  35              		.cfi_def_cfa_offset 16
  36 0004 00AF     		add	r7, sp, #0
  37              		.cfi_def_cfa_register 7
  38 0006 0346     		mov	r3, r0
  39 0008 FB71     		strb	r3, [r7, #7]
1628:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
  40              		.loc 1 1628 0
  41 000a FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
  42 000c 03F01F02 		and	r2, r3, #31
  43 0010 0749     		ldr	r1, .L2
  44 0012 97F90730 		ldrsb	r3, [r7, #7]
  45 0016 5B09     		lsrs	r3, r3, #5
  46 0018 0120     		movs	r0, #1
  47 001a 00FA02F2 		lsl	r2, r0, r2
  48 001e 41F82320 		str	r2, [r1, r3, lsl #2]
1629:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
  49              		.loc 1 1629 0
  50 0022 00BF     		nop
  51 0024 0C37     		adds	r7, r7, #12
  52              		.cfi_def_cfa_offset 4
  53 0026 BD46     		mov	sp, r7
  54              		.cfi_def_cfa_register 13
  55              		@ sp needed
  56 0028 5DF8047B 		ldr	r7, [sp], #4
  57              		.cfi_restore 7
  58              		.cfi_def_cfa_offset 0
  59 002c 7047     		bx	lr
  60              	.L3:
  61 002e 00BF     		.align	2
  62              	.L2:
  63 0030 00E100E0 		.word	-536813312
  64              		.cfi_endproc
  65              	.LFE108:
  67              		.align	1
  68              		.syntax unified
  69              		.thumb
  70              		.thumb_func
  71              		.fpu fpv4-sp-d16
  73              	NVIC_DisableIRQ:
  74              	.LFB109:
1630:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1631:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** 
1632:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** /**
1633:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \brief   Disable External Interrupt
1634:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \details Disables a device-specific interrupt in the NVIC interrupt controller.
1635:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
1636:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****  */
1637:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1638:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** {
  75              		.loc 1 1638 0
  76              		.cfi_startproc
  77              		@ args = 0, pretend = 0, frame = 8
  78              		@ frame_needed = 1, uses_anonymous_args = 0
  79              		@ link register save eliminated.
  80 0034 80B4     		push	{r7}
  81              		.cfi_def_cfa_offset 4
  82              		.cfi_offset 7, -4
  83 0036 83B0     		sub	sp, sp, #12
  84              		.cfi_def_cfa_offset 16
  85 0038 00AF     		add	r7, sp, #0
  86              		.cfi_def_cfa_register 7
  87 003a 0346     		mov	r3, r0
  88 003c FB71     		strb	r3, [r7, #7]
1639:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h ****   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
  89              		.loc 1 1639 0
  90 003e FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
  91 0040 03F01F02 		and	r2, r3, #31
  92 0044 0749     		ldr	r1, .L5
  93 0046 97F90730 		ldrsb	r3, [r7, #7]
  94 004a 5B09     		lsrs	r3, r3, #5
  95 004c 0120     		movs	r0, #1
  96 004e 00FA02F2 		lsl	r2, r0, r2
  97 0052 2033     		adds	r3, r3, #32
  98 0054 41F82320 		str	r2, [r1, r3, lsl #2]
1640:C:\Users\lenovo\Desktop\MSP-20210417\MSP-20210417\User-MSP432-20210417\CH04-GPIO\GPIO-Output-DirectAddress(MSP432)-20210406\02_CPU\core_cm4.h **** }
  99              		.loc 1 1640 0
 100 0058 00BF     		nop
 101 005a 0C37     		adds	r7, r7, #12
 102              		.cfi_def_cfa_offset 4
 103 005c BD46     		mov	sp, r7
 104              		.cfi_def_cfa_register 13
 105              		@ sp needed
 106 005e 5DF8047B 		ldr	r7, [sp], #4
 107              		.cfi_restore 7
 108              		.cfi_def_cfa_offset 0
 109 0062 7047     		bx	lr
 110              	.L6:
 111              		.align	2
 112              	.L5:
 113 0064 00E100E0 		.word	-536813312
 114              		.cfi_endproc
 115              	.LFE109:
 117              		.data
 118              		.align	2
 121              	UART_ARR:
 122 0000 00100040 		.word	1073745920
 123 0004 00140040 		.word	1073746944
 124 0008 00180040 		.word	1073747968
 125 000c 001C0040 		.word	1073748992
 126              		.section	.rodata
 127              		.align	2
 130              	table_irq_uart:
 131 0000 10       		.byte	16
 132 0001 11       		.byte	17
 133 0002 12       		.byte	18
 134 0003 13       		.byte	19
 135              		.global	BRSxS
 136              		.data
 137              		.align	2
 140              	BRSxS:
 141 0010 0000     		.short	0
 142 0012 3400     		.short	52
 143 0014 4700     		.short	71
 144 0016 5300     		.short	83
 145 0018 6400     		.short	100
 146 001a 7D00     		.short	125
 147 001c 8F00     		.short	143
 148 001e A700     		.short	167
 149 0020 D600     		.short	214
 150 0022 DE00     		.short	222
 151 0024 FA00     		.short	250
 152 0026 2C01     		.short	300
 153 0028 4D01     		.short	333
 154 002a 6501     		.short	357
 155 002c 7701     		.short	375
 156 002e 9001     		.short	400
 157 0030 AC01     		.short	428
 158 0032 B501     		.short	437
 159 0034 F401     		.short	500
 160 0036 3B02     		.short	571
 161 0038 5802     		.short	600
 162 003a 7102     		.short	625
 163 003c 8302     		.short	643
 164 003e 9A02     		.short	666
 165 0040 BC02     		.short	700
 166 0042 CA02     		.short	714
 167 0044 EE02     		.short	750
 168 0046 1203     		.short	786
 169 0048 2003     		.short	800
 170 004a 4103     		.short	833
 171 004c 4E03     		.short	846
 172 004e 5903     		.short	857
 173 0050 6B03     		.short	875
 174 0052 8403     		.short	900
 175 0054 9503     		.short	917
 176 0056 A003     		.short	928
 177              		.global	ValBRSxS
 178              		.align	2
 181              	ValBRSxS:
 182 0058 00       		.byte	0
 183 0059 01       		.byte	1
 184 005a 02       		.byte	2
 185 005b 04       		.byte	4
 186 005c 08       		.byte	8
 187 005d 10       		.byte	16
 188 005e 20       		.byte	32
 189 005f 11       		.byte	17
 190 0060 21       		.byte	33
 191 0061 22       		.byte	34
 192 0062 44       		.byte	68
 193 0063 25       		.byte	37
 194 0064 49       		.byte	73
 195 0065 4A       		.byte	74
 196 0066 52       		.byte	82
 197 0067 92       		.byte	-110
 198 0068 53       		.byte	83
 199 0069 55       		.byte	85
 200 006a AA       		.byte	-86
 201 006b 6B       		.byte	107
 202 006c AD       		.byte	-83
 203 006d B5       		.byte	-75
 204 006e B6       		.byte	-74
 205 006f D6       		.byte	-42
 206 0070 B7       		.byte	-73
 207 0071 BB       		.byte	-69
 208 0072 DD       		.byte	-35
 209 0073 ED       		.byte	-19
 210 0074 EE       		.byte	-18
 211 0075 BF       		.byte	-65
 212 0076 DF       		.byte	-33
 213 0077 EF       		.byte	-17
 214 0078 F7       		.byte	-9
 215 0079 FB       		.byte	-5
 216 007a FD       		.byte	-3
 217 007b FE       		.byte	-2
 218              		.global	__aeabi_ui2d
 219              		.global	__aeabi_ddiv
 220              		.global	__aeabi_d2uiz
 221              		.global	__aeabi_i2d
 222              		.global	__aeabi_dsub
 223              		.global	__aeabi_dmul
 224              		.text
 225              		.align	1
 226              		.global	uart_init
 227              		.syntax unified
 228              		.thumb
 229              		.thumb_func
 230              		.fpu fpv4-sp-d16
 232              	uart_init:
 233              	.LFB123:
 234              		.file 2 "srcc/uart.c"
   1:srcc/uart.c   **** //======================================================================
   2:srcc/uart.c   **** //ÎÄ¼þÃû³Æ£ºuart.c
   3:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£ºuartµ×²ãÇý¶¯¹¹¼þÔ´ÎÄ¼þ
   4:srcc/uart.c   **** //°æÈ¨ËùÓÐ£ºËÕÖÝ´óÑ§·ÉË¼¿¨¶ûÇ¶ÈëÊ½ÖÐÐÄ(sumcu.suda.edu.cn)
   5:srcc/uart.c   **** //¸üÐÂ¼ÇÂ¼£º2017-11-01 V1.0
   6:srcc/uart.c   **** //======================================================================
   7:srcc/uart.c   **** #include "uart.h"
   8:srcc/uart.c   **** 
   9:srcc/uart.c   **** 
  10:srcc/uart.c   **** //=====´®¿ÚµØÖ·Ó³Éä====
  11:srcc/uart.c   **** static const EUSCI_A_Type* UART_ARR[4] = {(EUSCI_A_Type*)EUSCI_A0_BASE,(EUSCI_A_Type*) EUSCI_A1_BAS
  12:srcc/uart.c   **** //====¶¨Òå´®¿ÚIRQºÅ¶ÔÓ¦±í====
  13:srcc/uart.c   **** static const IRQn_Type table_irq_uart[4] = {EUSCIA0_IRQn, EUSCIA1_IRQn, EUSCIA2_IRQn,EUSCIA3_IRQn};
  14:srcc/uart.c   **** //=====1.0*fBRCLK/(16*baud_rate)µÄÐ¡Êý²¿·ÖµÄËùÓÐ¿ÉÄÜÈ¡Öµ*1000µÄ¼¯ºÏ=====
  15:srcc/uart.c   **** uint16_t BRSxS[]={ 0, 52, 71, 83,100,125,143,167,214,
  16:srcc/uart.c   **** 		         222,250,300,333,357,375,400,428,437,
  17:srcc/uart.c   **** 				 500,571,600,625,643,666,700,714,750,
  18:srcc/uart.c   **** 				 786,800,833,846,857,875,900,917,928} ;
  19:srcc/uart.c   **** 
  20:srcc/uart.c   **** //=====Óë1.0*fBRCLK/(16*baud_rate)Ð¡Êý²¿·Ö¶ÔÓ¦µÄUCBRFx¸³ÖµµÄÓ³ÉäÖµ=====
  21:srcc/uart.c   **** uint8_t ValBRSxS[]={0x00,0x01,0x02,0x04,0X08,0x10,0x20,0x11,0x21,
  22:srcc/uart.c   ****                     0x22,0x44,0x25,0x49,0x4A,0x52,0x92,0x53,0x55,
  23:srcc/uart.c   ****                     0xAA,0x6B,0XAD,0XB5,0XB6,0XD6,0XB7,0XBB,0XDD,
  24:srcc/uart.c   ****                     0XED,0XEE,0XBF,0XDF,0XEF,0XF7,0XFB,0XFD,0XFE} ;
  25:srcc/uart.c   **** //*****************************************************************************
  26:srcc/uart.c   **** //ÄÚ²¿º¯ÊýÉùÃ÷
  27:srcc/uart.c   **** uint8_t uart_is_uartNo(uint8_t uartNo);
  28:srcc/uart.c   **** uint8_t BRSxSel(double fra);
  29:srcc/uart.c   **** 
  30:srcc/uart.c   **** //======================================================================
  31:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_init
  32:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º³õÊ¼»¯uartÄ£¿é
  33:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
  34:srcc/uart.c   **** //          baud:²¨ÌØÂÊ£º300¡¢600¡¢1200¡¢2400¡¢4800¡¢9600¡¢19200¡¢115200...
  35:srcc/uart.c   **** //º¯Êý·µ»Ø£ºÎÞ
  36:srcc/uart.c   **** //======================================================================
  37:srcc/uart.c   **** void uart_init(uint8_t uartNo, uint32_t baud_rate)
  38:srcc/uart.c   **** {
 235              		.loc 2 38 0
 236              		.cfi_startproc
 237              		@ args = 0, pretend = 0, frame = 40
 238              		@ frame_needed = 1, uses_anonymous_args = 0
 239 0068 90B5     		push	{r4, r7, lr}
 240              		.cfi_def_cfa_offset 12
 241              		.cfi_offset 4, -12
 242              		.cfi_offset 7, -8
 243              		.cfi_offset 14, -4
 244 006a 8BB0     		sub	sp, sp, #44
 245              		.cfi_def_cfa_offset 56
 246 006c 00AF     		add	r7, sp, #0
 247              		.cfi_def_cfa_register 7
 248 006e 0346     		mov	r3, r0
 249 0070 3960     		str	r1, [r7]
 250 0072 FB71     		strb	r3, [r7, #7]
  39:srcc/uart.c   **** 	//¾Ö²¿±äÁ¿ÉùÃ÷
  40:srcc/uart.c   **** 	double sbr,fraction;
  41:srcc/uart.c   **** 	uint32_t abr,brfx;
  42:srcc/uart.c   **** 	EUSCI_A_Type* uartch;//uartchÎªUARTMemMapPtrÀàÐÍÖ¸Õë
  43:srcc/uart.c   **** 
  44:srcc/uart.c   **** 	//ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
  45:srcc/uart.c   ****     if(!uart_is_uartNo(uartNo))
 251              		.loc 2 45 0
 252 0074 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 253 0076 1846     		mov	r0, r3
 254 0078 FFF7FEFF 		bl	uart_is_uartNo
 255 007c 0346     		mov	r3, r0
 256 007e 002B     		cmp	r3, #0
 257 0080 00F0E080 		beq	.L16
  46:srcc/uart.c   ****     {
  47:srcc/uart.c   ****     	return ;
  48:srcc/uart.c   ****     }
  49:srcc/uart.c   ****     uartch=(EUSCI_A_Type*)UART_ARR[uartNo];//¸ù¾Ý´øÈë²ÎÊýuartNo£¬¸ø¾Ö²¿±äÁ¿uartch¸³Öµ
 258              		.loc 2 49 0
 259 0084 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 260 0086 744A     		ldr	r2, .L17+8
 261 0088 52F82330 		ldr	r3, [r2, r3, lsl #2]
 262 008c 7B62     		str	r3, [r7, #36]
  50:srcc/uart.c   **** 
  51:srcc/uart.c   ****     //Ê±ÖÓÅäÖÃ
  52:srcc/uart.c   ****     CS->KEY= 0x695A;                          //½âËøCSÄ£¿é£¬½øÐÐ×¢²á
 263              		.loc 2 52 0
 264 008e 734B     		ldr	r3, .L17+12
 265 0090 46F65A12 		movw	r2, #26970
 266 0094 1A60     		str	r2, [r3]
  53:srcc/uart.c   **** 
  54:srcc/uart.c   **** 
  55:srcc/uart.c   **** 
  56:srcc/uart.c   **** 
  57:srcc/uart.c   **** //    CS->CTL0|= CS_CTL0_DCORSEL_3;            //½«DCOÉèÖÃÎª12MHz£¨±ê³ÆÖµ£¬8-16MHz·¶Î§µÄÖÐÐÄ£©
  58:srcc/uart.c   **** //    CS->CTL1|= CS_CTL1_SELA_2 | CS_CTL1_SELS_3 | CS_CTL1_SELM_3;//Ñ¡Ôñ ACLK = REFO, SMCLK = MCLK 
  59:srcc/uart.c   **** 
  60:srcc/uart.c   ****     //
  61:srcc/uart.c   ****     CS->CTL1|=CS_CTL1_DIVS_2;
 267              		.loc 2 61 0
 268 0096 714B     		ldr	r3, .L17+12
 269 0098 9B68     		ldr	r3, [r3, #8]
 270 009a 704A     		ldr	r2, .L17+12
 271 009c 43F00053 		orr	r3, r3, #536870912
 272 00a0 9360     		str	r3, [r2, #8]
  62:srcc/uart.c   **** 
  63:srcc/uart.c   **** 
  64:srcc/uart.c   **** 
  65:srcc/uart.c   ****     CS->KEY= 0;                             //Ëø¶¨CSÄ£¿éÒÔ±ÜÃâÒâÍâµÄ·ÃÎÊ
 273              		.loc 2 65 0
 274 00a2 6E4B     		ldr	r3, .L17+12
 275 00a4 0022     		movs	r2, #0
 276 00a6 1A60     		str	r2, [r3]
  66:srcc/uart.c   **** 
  67:srcc/uart.c   **** 	//ÒÀ¾ÝÑ¡ÔñÅäÖÃUARTxµÄ¶ÔÓ¦Òý½Å
  68:srcc/uart.c   ****     switch(uartNo)
 277              		.loc 2 68 0
 278 00a8 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 279 00aa 032B     		cmp	r3, #3
 280 00ac 4ED8     		bhi	.L10
 281 00ae 01A2     		adr	r2, .L12
 282 00b0 52F823F0 		ldr	pc, [r2, r3, lsl #2]
 283              		.p2align 2
 284              	.L12:
 285 00b4 C5000000 		.word	.L11+1
 286 00b8 E7000000 		.word	.L13+1
 287 00bc 09010000 		.word	.L14+1
 288 00c0 2B010000 		.word	.L15+1
 289              		.p2align 1
 290              	.L11:
  69:srcc/uart.c   ****     {
  70:srcc/uart.c   ****     	case UART_0: P1SEL0|=BIT2 | BIT3; P1SEL1&=(~BIT2)&(~BIT3);break;  //P1.2 Òý½Å¹¦ÄÜÉèÖÃÎªRX,P1.3
 291              		.loc 2 70 0
 292 00c4 664B     		ldr	r3, .L17+16
 293 00c6 1B78     		ldrb	r3, [r3]
 294 00c8 DBB2     		uxtb	r3, r3
 295 00ca 654A     		ldr	r2, .L17+16
 296 00cc 43F00C03 		orr	r3, r3, #12
 297 00d0 DBB2     		uxtb	r3, r3
 298 00d2 1370     		strb	r3, [r2]
 299 00d4 634B     		ldr	r3, .L17+20
 300 00d6 1B78     		ldrb	r3, [r3]
 301 00d8 DBB2     		uxtb	r3, r3
 302 00da 624A     		ldr	r2, .L17+20
 303 00dc 23F00C03 		bic	r3, r3, #12
 304 00e0 DBB2     		uxtb	r3, r3
 305 00e2 1370     		strb	r3, [r2]
 306 00e4 32E0     		b	.L10
 307              	.L13:
  71:srcc/uart.c   ****     	case UART_1: P2SEL0|=BIT2 | BIT3; P2SEL1&=(~BIT2)&(~BIT3);break;
 308              		.loc 2 71 0
 309 00e6 604B     		ldr	r3, .L17+24
 310 00e8 1B78     		ldrb	r3, [r3]
 311 00ea DBB2     		uxtb	r3, r3
 312 00ec 5E4A     		ldr	r2, .L17+24
 313 00ee 43F00C03 		orr	r3, r3, #12
 314 00f2 DBB2     		uxtb	r3, r3
 315 00f4 1370     		strb	r3, [r2]
 316 00f6 5D4B     		ldr	r3, .L17+28
 317 00f8 1B78     		ldrb	r3, [r3]
 318 00fa DBB2     		uxtb	r3, r3
 319 00fc 5B4A     		ldr	r2, .L17+28
 320 00fe 23F00C03 		bic	r3, r3, #12
 321 0102 DBB2     		uxtb	r3, r3
 322 0104 1370     		strb	r3, [r2]
 323 0106 21E0     		b	.L10
 324              	.L14:
  72:srcc/uart.c   ****     	case UART_2: P3SEL0|=BIT2 | BIT3; P3SEL1&=(~BIT2)&(~BIT3);break;
 325              		.loc 2 72 0
 326 0108 594B     		ldr	r3, .L17+32
 327 010a 1B78     		ldrb	r3, [r3]
 328 010c DBB2     		uxtb	r3, r3
 329 010e 584A     		ldr	r2, .L17+32
 330 0110 43F00C03 		orr	r3, r3, #12
 331 0114 DBB2     		uxtb	r3, r3
 332 0116 1370     		strb	r3, [r2]
 333 0118 564B     		ldr	r3, .L17+36
 334 011a 1B78     		ldrb	r3, [r3]
 335 011c DBB2     		uxtb	r3, r3
 336 011e 554A     		ldr	r2, .L17+36
 337 0120 23F00C03 		bic	r3, r3, #12
 338 0124 DBB2     		uxtb	r3, r3
 339 0126 1370     		strb	r3, [r2]
 340 0128 10E0     		b	.L10
 341              	.L15:
  73:srcc/uart.c   ****     	case UART_3: P9SEL0|=BIT6 | BIT7; P9SEL1&=(~BIT6)&(~BIT7);break;
 342              		.loc 2 73 0
 343 012a 534B     		ldr	r3, .L17+40
 344 012c 1B78     		ldrb	r3, [r3]
 345 012e DBB2     		uxtb	r3, r3
 346 0130 514A     		ldr	r2, .L17+40
 347 0132 63F03F03 		orn	r3, r3, #63
 348 0136 DBB2     		uxtb	r3, r3
 349 0138 1370     		strb	r3, [r2]
 350 013a 504B     		ldr	r3, .L17+44
 351 013c 1B78     		ldrb	r3, [r3]
 352 013e DBB2     		uxtb	r3, r3
 353 0140 4E4A     		ldr	r2, .L17+44
 354 0142 03F03F03 		and	r3, r3, #63
 355 0146 DBB2     		uxtb	r3, r3
 356 0148 1370     		strb	r3, [r2]
 357 014a 00BF     		nop
 358              	.L10:
  74:srcc/uart.c   ****     }
  75:srcc/uart.c   **** 
  76:srcc/uart.c   **** 
  77:srcc/uart.c   ****     // UARTÅäÖÃ
  78:srcc/uart.c   ****     uartch->CTLW0|= UCSWRST;                   //Ê¹ÄÜÈí¼þ¸´Î»
 359              		.loc 2 78 0
 360 014c 7B6A     		ldr	r3, [r7, #36]
 361 014e 1B88     		ldrh	r3, [r3]	@ movhi
 362 0150 9BB2     		uxth	r3, r3
 363 0152 43F00103 		orr	r3, r3, #1
 364 0156 9AB2     		uxth	r2, r3
 365 0158 7B6A     		ldr	r3, [r7, #36]
 366 015a 1A80     		strh	r2, [r3]	@ movhi
  79:srcc/uart.c   ****     uartch->CTLW0|= UCSSEL__SMCLK;             //BRCLKÔ´Ê±ÖÓÑ¡ÔñSMCLK
 367              		.loc 2 79 0
 368 015c 7B6A     		ldr	r3, [r7, #36]
 369 015e 1B88     		ldrh	r3, [r3]	@ movhi
 370 0160 9BB2     		uxth	r3, r3
 371 0162 43F08003 		orr	r3, r3, #128
 372 0166 9AB2     		uxth	r2, r3
 373 0168 7B6A     		ldr	r3, [r7, #36]
 374 016a 1A80     		strh	r2, [r3]	@ movhi
  80:srcc/uart.c   **** 
  81:srcc/uart.c   ****     //²ÎÊýbaud_rateµÄÏà¹Ø¼ÆËã
  82:srcc/uart.c   ****     sbr=1.0*12000000/(16*baud_rate);							//Çósbr
 375              		.loc 2 82 0
 376 016c 3B68     		ldr	r3, [r7]
 377 016e 1B01     		lsls	r3, r3, #4
 378 0170 1846     		mov	r0, r3
 379 0172 FFF7FEFF 		bl	__aeabi_ui2d
 380              	.LVL0:
 381 0176 0346     		mov	r3, r0
 382 0178 0C46     		mov	r4, r1
 383 017a 1A46     		mov	r2, r3
 384 017c 2346     		mov	r3, r4
 385 017e 34A1     		adr	r1, .L17
 386 0180 D1E90001 		ldrd	r0, [r1]
 387 0184 FFF7FEFF 		bl	__aeabi_ddiv
 388              	.LVL1:
 389 0188 0346     		mov	r3, r0
 390 018a 0C46     		mov	r4, r1
 391 018c C7E90634 		strd	r3, [r7, #24]
  83:srcc/uart.c   ****     fraction=sbr-(uint16_t)sbr;								//ÇósbrµÄÐ¡Êý²¿·Ö
 392              		.loc 2 83 0
 393 0190 D7E90601 		ldrd	r0, [r7, #24]
 394 0194 FFF7FEFF 		bl	__aeabi_d2uiz
 395              	.LVL2:
 396 0198 0346     		mov	r3, r0
 397 019a 9BB2     		uxth	r3, r3
 398 019c 1846     		mov	r0, r3
 399 019e FFF7FEFF 		bl	__aeabi_i2d
 400              	.LVL3:
 401 01a2 0346     		mov	r3, r0
 402 01a4 0C46     		mov	r4, r1
 403 01a6 1A46     		mov	r2, r3
 404 01a8 2346     		mov	r3, r4
 405 01aa D7E90601 		ldrd	r0, [r7, #24]
 406 01ae FFF7FEFF 		bl	__aeabi_dsub
 407              	.LVL4:
 408 01b2 0346     		mov	r3, r0
 409 01b4 0C46     		mov	r4, r1
 410 01b6 C7E90434 		strd	r3, [r7, #16]
  84:srcc/uart.c   ****     abr=(uint16_t)sbr;										//ÇósbrµÄÕûÊý²¿·Ö
 411              		.loc 2 84 0
 412 01ba D7E90601 		ldrd	r0, [r7, #24]
 413 01be FFF7FEFF 		bl	__aeabi_d2uiz
 414              	.LVL5:
 415 01c2 0346     		mov	r3, r0
 416 01c4 9BB2     		uxth	r3, r3
 417 01c6 FB60     		str	r3, [r7, #12]
  85:srcc/uart.c   ****     brfx=(uint16_t)(fraction*16);							//¼ÆËãUCBRFxµÄÊýÖµ
 418              		.loc 2 85 0
 419 01c8 4FF00002 		mov	r2, #0
 420 01cc 2C4B     		ldr	r3, .L17+48
 421 01ce D7E90401 		ldrd	r0, [r7, #16]
 422 01d2 FFF7FEFF 		bl	__aeabi_dmul
 423              	.LVL6:
 424 01d6 0346     		mov	r3, r0
 425 01d8 0C46     		mov	r4, r1
 426 01da 1846     		mov	r0, r3
 427 01dc 2146     		mov	r1, r4
 428 01de FFF7FEFF 		bl	__aeabi_d2uiz
 429              	.LVL7:
 430 01e2 0346     		mov	r3, r0
 431 01e4 9BB2     		uxth	r3, r3
 432 01e6 BB60     		str	r3, [r7, #8]
  86:srcc/uart.c   **** 
  87:srcc/uart.c   ****     uartch->BRW=abr;							//ÕûÊý²¿·Ö¸³¸øBRW
 433              		.loc 2 87 0
 434 01e8 FB68     		ldr	r3, [r7, #12]
 435 01ea 9AB2     		uxth	r2, r3
 436 01ec 7B6A     		ldr	r3, [r7, #36]
 437 01ee DA80     		strh	r2, [r3, #6]	@ movhi
  88:srcc/uart.c   ****     uartch->MCTLW=(BRSxSel(fraction)<<UCBRS_OFS)|(brfx<<UCBRF_OFS)|(UCOS16<<UCOS16_OFS);//¹ý²ÉÑùÄ£Ê
 438              		.loc 2 88 0
 439 01f0 97ED040B 		vldr.64	d0, [r7, #16]
 440 01f4 FFF7FEFF 		bl	BRSxSel
 441 01f8 0346     		mov	r3, r0
 442 01fa 9BB2     		uxth	r3, r3
 443 01fc 1B02     		lsls	r3, r3, #8
 444 01fe 9AB2     		uxth	r2, r3
 445 0200 BB68     		ldr	r3, [r7, #8]
 446 0202 9BB2     		uxth	r3, r3
 447 0204 1B01     		lsls	r3, r3, #4
 448 0206 9BB2     		uxth	r3, r3
 449 0208 1343     		orrs	r3, r3, r2
 450 020a 9BB2     		uxth	r3, r3
 451 020c 43F00103 		orr	r3, r3, #1
 452 0210 9AB2     		uxth	r2, r3
 453 0212 7B6A     		ldr	r3, [r7, #36]
 454 0214 1A81     		strh	r2, [r3, #8]	@ movhi
  89:srcc/uart.c   ****     uartch->CTLW0&= ~UCSWRST;                   //½ûÓÃÈí¼þ¸´Î»
 455              		.loc 2 89 0
 456 0216 7B6A     		ldr	r3, [r7, #36]
 457 0218 1B88     		ldrh	r3, [r3]	@ movhi
 458 021a 9BB2     		uxth	r3, r3
 459 021c 23F00103 		bic	r3, r3, #1
 460 0220 9AB2     		uxth	r2, r3
 461 0222 7B6A     		ldr	r3, [r7, #36]
 462 0224 1A80     		strh	r2, [r3]	@ movhi
  90:srcc/uart.c   ****     uartch->IE&=~UCTXIE;//½ûÓÃ´®¿Ú·¢ËÍÖÐ¶Ï
 463              		.loc 2 90 0
 464 0226 7B6A     		ldr	r3, [r7, #36]
 465 0228 5B8B     		ldrh	r3, [r3, #26]	@ movhi
 466 022a 9BB2     		uxth	r3, r3
 467 022c 23F00203 		bic	r3, r3, #2
 468 0230 9AB2     		uxth	r2, r3
 469 0232 7B6A     		ldr	r3, [r7, #36]
 470 0234 5A83     		strh	r2, [r3, #26]	@ movhi
  91:srcc/uart.c   ****     NVIC_EnableIRQ(table_irq_uart[uartNo]);//ÔÚNVICÄ£¿éÖÐÊ¹ÄÜEUSCIAÖÐ¶Ï
 471              		.loc 2 91 0
 472 0236 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 473 0238 124A     		ldr	r2, .L17+52
 474 023a D356     		ldrsb	r3, [r2, r3]
 475 023c 1846     		mov	r0, r3
 476 023e FFF7DFFE 		bl	NVIC_EnableIRQ
 477 0242 00E0     		b	.L7
 478              	.L16:
  47:srcc/uart.c   ****     }
 479              		.loc 2 47 0
 480 0244 00BF     		nop
 481              	.L7:
  92:srcc/uart.c   **** }
 482              		.loc 2 92 0
 483 0246 2C37     		adds	r7, r7, #44
 484              		.cfi_def_cfa_offset 12
 485 0248 BD46     		mov	sp, r7
 486              		.cfi_def_cfa_register 13
 487              		@ sp needed
 488 024a 90BD     		pop	{r4, r7, pc}
 489              	.L18:
 490 024c AFF30080 		.align	3
 491              	.L17:
 492 0250 00000000 		.word	0
 493 0254 60E36641 		.word	1097261920
 494 0258 00000000 		.word	UART_ARR
 495 025c 00040140 		.word	1073808384
 496 0260 0A4C0040 		.word	1073761290
 497 0264 0C4C0040 		.word	1073761292
 498 0268 0B4C0040 		.word	1073761291
 499 026c 0D4C0040 		.word	1073761293
 500 0270 2A4C0040 		.word	1073761322
 501 0274 2C4C0040 		.word	1073761324
 502 0278 8A4C0040 		.word	1073761418
 503 027c 8C4C0040 		.word	1073761420
 504 0280 00003040 		.word	1076887552
 505 0284 00000000 		.word	table_irq_uart
 506              		.cfi_endproc
 507              	.LFE123:
 509              		.align	1
 510              		.global	uart_send1
 511              		.syntax unified
 512              		.thumb
 513              		.thumb_func
 514              		.fpu fpv4-sp-d16
 516              	uart_send1:
 517              	.LFB124:
  93:srcc/uart.c   **** //======================================================================
  94:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_send1
  95:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
  96:srcc/uart.c   **** //          ch:Òª·¢ËÍµÄ×Ö½Ú
  97:srcc/uart.c   **** //º¯Êý·µ»Ø£ºº¯ÊýÖ´ÐÐ×´Ì¬£º1=·¢ËÍ³É¹¦£»0=·¢ËÍÊ§°Ü¡£
  98:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º´®ÐÐ·¢ËÍ1¸ö×Ö½Ú
  99:srcc/uart.c   **** //======================================================================
 100:srcc/uart.c   **** uint8_t uart_send1(uint8_t uartNo, uint8_t ch)
 101:srcc/uart.c   **** {
 518              		.loc 2 101 0
 519              		.cfi_startproc
 520              		@ args = 0, pretend = 0, frame = 16
 521              		@ frame_needed = 1, uses_anonymous_args = 0
 522 0288 80B5     		push	{r7, lr}
 523              		.cfi_def_cfa_offset 8
 524              		.cfi_offset 7, -8
 525              		.cfi_offset 14, -4
 526 028a 84B0     		sub	sp, sp, #16
 527              		.cfi_def_cfa_offset 24
 528 028c 00AF     		add	r7, sp, #0
 529              		.cfi_def_cfa_register 7
 530 028e 0346     		mov	r3, r0
 531 0290 0A46     		mov	r2, r1
 532 0292 FB71     		strb	r3, [r7, #7]
 533 0294 1346     		mov	r3, r2
 534 0296 BB71     		strb	r3, [r7, #6]
 102:srcc/uart.c   **** 	uint32_t t;
 103:srcc/uart.c   ****     EUSCI_A_Type* uartch; //uartchÎªEUSCI_A_Type*ÀàÐÍÖ¸Õë
 104:srcc/uart.c   **** 
 105:srcc/uart.c   ****     //ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 106:srcc/uart.c   **** 	if(!uart_is_uartNo(uartNo))
 535              		.loc 2 106 0
 536 0298 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 537 029a 1846     		mov	r0, r3
 538 029c FFF7FEFF 		bl	uart_is_uartNo
 539 02a0 0346     		mov	r3, r0
 540 02a2 002B     		cmp	r3, #0
 541 02a4 01D1     		bne	.L20
 107:srcc/uart.c   **** 	{
 108:srcc/uart.c   **** 		return 0;
 542              		.loc 2 108 0
 543 02a6 0023     		movs	r3, #0
 544 02a8 23E0     		b	.L21
 545              	.L20:
 109:srcc/uart.c   **** 	}
 110:srcc/uart.c   **** 	uartch=(EUSCI_A_Type*)UART_ARR[uartNo];//»ñÈ¡UARTx»ùµØÖ·
 546              		.loc 2 110 0
 547 02aa FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 548 02ac 134A     		ldr	r2, .L27
 549 02ae 52F82330 		ldr	r3, [r2, r3, lsl #2]
 550 02b2 BB60     		str	r3, [r7, #8]
 111:srcc/uart.c   **** 
 112:srcc/uart.c   **** 	 for (t = 0; t < 0xFBBB; t++)//²éÑ¯Ö¸¶¨´ÎÊý
 551              		.loc 2 112 0
 552 02b4 0023     		movs	r3, #0
 553 02b6 FB60     		str	r3, [r7, #12]
 554 02b8 0EE0     		b	.L22
 555              	.L25:
 113:srcc/uart.c   **** 	{
 114:srcc/uart.c   **** 	 //·¢ËÍ»º³åÇøÎª¿ÕÔò·¢ËÍÊý¾Ý
 115:srcc/uart.c   **** 	 if(uartch->IFG&UCTXIFG)
 556              		.loc 2 115 0
 557 02ba BB68     		ldr	r3, [r7, #8]
 558 02bc 9B8B     		ldrh	r3, [r3, #28]	@ movhi
 559 02be 9BB2     		uxth	r3, r3
 560 02c0 03F00203 		and	r3, r3, #2
 561 02c4 002B     		cmp	r3, #0
 562 02c6 04D0     		beq	.L23
 116:srcc/uart.c   **** 	 {
 117:srcc/uart.c   **** 		 uartch->TXBUF= ch;//½«chÖµËÍÈë·¢ËÍ»º³åÇø
 563              		.loc 2 117 0
 564 02c8 BB79     		ldrb	r3, [r7, #6]	@ zero_extendqisi2
 565 02ca 9AB2     		uxth	r2, r3
 566 02cc BB68     		ldr	r3, [r7, #8]
 567 02ce DA81     		strh	r2, [r3, #14]	@ movhi
 118:srcc/uart.c   **** 		 break;
 568              		.loc 2 118 0
 569 02d0 07E0     		b	.L24
 570              	.L23:
 112:srcc/uart.c   **** 	{
 571              		.loc 2 112 0
 572 02d2 FB68     		ldr	r3, [r7, #12]
 573 02d4 0133     		adds	r3, r3, #1
 574 02d6 FB60     		str	r3, [r7, #12]
 575              	.L22:
 112:srcc/uart.c   **** 	{
 576              		.loc 2 112 0 is_stmt 0
 577 02d8 FB68     		ldr	r3, [r7, #12]
 578 02da 4FF6BA32 		movw	r2, #64442
 579 02de 9342     		cmp	r3, r2
 580 02e0 EBD9     		bls	.L25
 581              	.L24:
 119:srcc/uart.c   **** 	 }
 120:srcc/uart.c   **** 	}
 121:srcc/uart.c   **** 	 //½áÊøÅÐ¶Ï
 122:srcc/uart.c   **** 	 if (t >= 0xFBBB)
 582              		.loc 2 122 0 is_stmt 1
 583 02e2 FB68     		ldr	r3, [r7, #12]
 584 02e4 4FF6BA32 		movw	r2, #64442
 585 02e8 9342     		cmp	r3, r2
 586 02ea 01D9     		bls	.L26
 123:srcc/uart.c   **** 		 return 0; //·¢ËÍ³¬Ê±£¬·¢ËÍÊ§°Ü
 587              		.loc 2 123 0
 588 02ec 0023     		movs	r3, #0
 589 02ee 00E0     		b	.L21
 590              	.L26:
 124:srcc/uart.c   **** 	 else
 125:srcc/uart.c   **** 		 return 1; //³É¹¦·¢ËÍ
 591              		.loc 2 125 0
 592 02f0 0123     		movs	r3, #1
 593              	.L21:
 126:srcc/uart.c   **** }
 594              		.loc 2 126 0
 595 02f2 1846     		mov	r0, r3
 596 02f4 1037     		adds	r7, r7, #16
 597              		.cfi_def_cfa_offset 8
 598 02f6 BD46     		mov	sp, r7
 599              		.cfi_def_cfa_register 13
 600              		@ sp needed
 601 02f8 80BD     		pop	{r7, pc}
 602              	.L28:
 603 02fa 00BF     		.align	2
 604              	.L27:
 605 02fc 00000000 		.word	UART_ARR
 606              		.cfi_endproc
 607              	.LFE124:
 609              		.align	1
 610              		.global	uart_sendN
 611              		.syntax unified
 612              		.thumb
 613              		.thumb_func
 614              		.fpu fpv4-sp-d16
 616              	uart_sendN:
 617              	.LFB125:
 127:srcc/uart.c   **** 
 128:srcc/uart.c   **** //======================================================================
 129:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_sendN
 130:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 131:srcc/uart.c   **** //         buff: ·¢ËÍ»º³åÇø
 132:srcc/uart.c   **** //         len:·¢ËÍ³¤¶È
 133:srcc/uart.c   **** //º¯Êý·µ»Ø£º º¯ÊýÖ´ÐÐ×´Ì¬£º1=·¢ËÍ³É¹¦£»0=·¢ËÍÊ§°Ü
 134:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º´®ÐÐ ½ÓÊÕn¸ö×Ö½Ú
 135:srcc/uart.c   **** //======================================================================
 136:srcc/uart.c   **** uint8_t uart_sendN(uint8_t uartNo ,uint16_t len ,uint8_t* buff)
 137:srcc/uart.c   **** {
 618              		.loc 2 137 0
 619              		.cfi_startproc
 620              		@ args = 0, pretend = 0, frame = 16
 621              		@ frame_needed = 1, uses_anonymous_args = 0
 622 0300 80B5     		push	{r7, lr}
 623              		.cfi_def_cfa_offset 8
 624              		.cfi_offset 7, -8
 625              		.cfi_offset 14, -4
 626 0302 84B0     		sub	sp, sp, #16
 627              		.cfi_def_cfa_offset 24
 628 0304 00AF     		add	r7, sp, #0
 629              		.cfi_def_cfa_register 7
 630 0306 0346     		mov	r3, r0
 631 0308 3A60     		str	r2, [r7]
 632 030a FB71     		strb	r3, [r7, #7]
 633 030c 0B46     		mov	r3, r1	@ movhi
 634 030e BB80     		strh	r3, [r7, #4]	@ movhi
 138:srcc/uart.c   ****     uint16_t i;
 139:srcc/uart.c   **** 
 140:srcc/uart.c   ****     //ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 141:srcc/uart.c   ****     if(!uart_is_uartNo(uartNo))
 635              		.loc 2 141 0
 636 0310 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 637 0312 1846     		mov	r0, r3
 638 0314 FFF7FEFF 		bl	uart_is_uartNo
 639 0318 0346     		mov	r3, r0
 640 031a 002B     		cmp	r3, #0
 641 031c 01D1     		bne	.L30
 142:srcc/uart.c   ****     {
 143:srcc/uart.c   ****         return 0;
 642              		.loc 2 143 0
 643 031e 0023     		movs	r3, #0
 644 0320 1EE0     		b	.L31
 645              	.L30:
 144:srcc/uart.c   ****     }
 145:srcc/uart.c   **** 
 146:srcc/uart.c   ****     for (i = 0; i < len; i++)
 646              		.loc 2 146 0
 647 0322 0023     		movs	r3, #0
 648 0324 FB81     		strh	r3, [r7, #14]	@ movhi
 649 0326 0EE0     		b	.L32
 650              	.L35:
 147:srcc/uart.c   ****     {
 148:srcc/uart.c   ****         if (!uart_send1(uartNo, buff[i])) //·¢ËÍÒ»¸ö×Ö½ÚÊý¾Ý£¬Ê§°ÜÔòÌø³öÑ­»·
 651              		.loc 2 148 0
 652 0328 FB89     		ldrh	r3, [r7, #14]
 653 032a 3A68     		ldr	r2, [r7]
 654 032c 1344     		add	r3, r3, r2
 655 032e 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
 656 0330 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 657 0332 1146     		mov	r1, r2
 658 0334 1846     		mov	r0, r3
 659 0336 FFF7FEFF 		bl	uart_send1
 660 033a 0346     		mov	r3, r0
 661 033c 002B     		cmp	r3, #0
 662 033e 07D0     		beq	.L37
 146:srcc/uart.c   ****     {
 663              		.loc 2 146 0
 664 0340 FB89     		ldrh	r3, [r7, #14]
 665 0342 0133     		adds	r3, r3, #1
 666 0344 FB81     		strh	r3, [r7, #14]	@ movhi
 667              	.L32:
 146:srcc/uart.c   ****     {
 668              		.loc 2 146 0 is_stmt 0
 669 0346 FA89     		ldrh	r2, [r7, #14]
 670 0348 BB88     		ldrh	r3, [r7, #4]
 671 034a 9A42     		cmp	r2, r3
 672 034c ECD3     		bcc	.L35
 673 034e 00E0     		b	.L34
 674              	.L37:
 149:srcc/uart.c   ****         {
 150:srcc/uart.c   ****             break;
 675              		.loc 2 150 0 is_stmt 1
 676 0350 00BF     		nop
 677              	.L34:
 151:srcc/uart.c   ****         }
 152:srcc/uart.c   ****     }
 153:srcc/uart.c   ****     if(i<len)
 678              		.loc 2 153 0
 679 0352 FA89     		ldrh	r2, [r7, #14]
 680 0354 BB88     		ldrh	r3, [r7, #4]
 681 0356 9A42     		cmp	r2, r3
 682 0358 01D2     		bcs	.L36
 154:srcc/uart.c   ****         return 0;    //·¢ËÍ³ö´í
 683              		.loc 2 154 0
 684 035a 0023     		movs	r3, #0
 685 035c 00E0     		b	.L31
 686              	.L36:
 155:srcc/uart.c   ****     else
 156:srcc/uart.c   ****         return 1;    //·¢ËÍ³ö´í
 687              		.loc 2 156 0
 688 035e 0123     		movs	r3, #1
 689              	.L31:
 157:srcc/uart.c   **** }
 690              		.loc 2 157 0
 691 0360 1846     		mov	r0, r3
 692 0362 1037     		adds	r7, r7, #16
 693              		.cfi_def_cfa_offset 8
 694 0364 BD46     		mov	sp, r7
 695              		.cfi_def_cfa_register 13
 696              		@ sp needed
 697 0366 80BD     		pop	{r7, pc}
 698              		.cfi_endproc
 699              	.LFE125:
 701              		.align	1
 702              		.global	uart_send_string
 703              		.syntax unified
 704              		.thumb
 705              		.thumb_func
 706              		.fpu fpv4-sp-d16
 708              	uart_send_string:
 709              	.LFB126:
 158:srcc/uart.c   **** 
 159:srcc/uart.c   **** //======================================================================
 160:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_send_string
 161:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 162:srcc/uart.c   **** //          buff:Òª·¢ËÍµÄ×Ö·û´®µÄÊ×µØÖ·
 163:srcc/uart.c   **** //º¯Êý·µ»Ø£º º¯ÊýÖ´ÐÐ×´Ì¬£º1=·¢ËÍ³É¹¦£»0=·¢ËÍÊ§°Ü
 164:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º´ÓÖ¸¶¨UART¶Ë¿Ú·¢ËÍÒ»¸öÒÔ'\0'½áÊøµÄ×Ö·û´®
 165:srcc/uart.c   **** //======================================================================
 166:srcc/uart.c   **** uint8_t uart_send_string(uint8_t uartNo, void *buff)
 167:srcc/uart.c   **** {
 710              		.loc 2 167 0
 711              		.cfi_startproc
 712              		@ args = 0, pretend = 0, frame = 16
 713              		@ frame_needed = 1, uses_anonymous_args = 0
 714 0368 80B5     		push	{r7, lr}
 715              		.cfi_def_cfa_offset 8
 716              		.cfi_offset 7, -8
 717              		.cfi_offset 14, -4
 718 036a 84B0     		sub	sp, sp, #16
 719              		.cfi_def_cfa_offset 24
 720 036c 00AF     		add	r7, sp, #0
 721              		.cfi_def_cfa_register 7
 722 036e 0346     		mov	r3, r0
 723 0370 3960     		str	r1, [r7]
 724 0372 FB71     		strb	r3, [r7, #7]
 168:srcc/uart.c   ****     uint16_t i = 0;
 725              		.loc 2 168 0
 726 0374 0023     		movs	r3, #0
 727 0376 FB81     		strh	r3, [r7, #14]	@ movhi
 169:srcc/uart.c   ****     uint8_t *buff_ptr = (uint8_t *)buff;     //¶¨ÒåÖ¸ÕëÖ¸ÏòÒª·¢ËÍ×Ö·û´®Ê×µØÖ·
 728              		.loc 2 169 0
 729 0378 3B68     		ldr	r3, [r7]
 730 037a BB60     		str	r3, [r7, #8]
 170:srcc/uart.c   **** 
 171:srcc/uart.c   ****     //ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 172:srcc/uart.c   ****     if(!uart_is_uartNo(uartNo))
 731              		.loc 2 172 0
 732 037c FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 733 037e 1846     		mov	r0, r3
 734 0380 FFF7FEFF 		bl	uart_is_uartNo
 735 0384 0346     		mov	r3, r0
 736 0386 002B     		cmp	r3, #0
 737 0388 01D1     		bne	.L39
 173:srcc/uart.c   ****     {
 174:srcc/uart.c   ****         return 0;
 738              		.loc 2 174 0
 739 038a 0023     		movs	r3, #0
 740 038c 1AE0     		b	.L40
 741              	.L39:
 175:srcc/uart.c   ****     }
 176:srcc/uart.c   **** 
 177:srcc/uart.c   ****     for(i = 0; buff_ptr[i] != '\0'; i++)   //±éÀú×Ö·û´®ÀïµÄ×Ö·û
 742              		.loc 2 177 0
 743 038e 0023     		movs	r3, #0
 744 0390 FB81     		strh	r3, [r7, #14]	@ movhi
 745 0392 10E0     		b	.L41
 746              	.L43:
 178:srcc/uart.c   ****     {
 179:srcc/uart.c   ****         if (!uart_send1(uartNo,buff_ptr[i]))//·¢ËÍÖ¸Õë¶ÔÓ¦µÄ×Ö·û
 747              		.loc 2 179 0
 748 0394 FB89     		ldrh	r3, [r7, #14]
 749 0396 BA68     		ldr	r2, [r7, #8]
 750 0398 1344     		add	r3, r3, r2
 751 039a 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
 752 039c FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 753 039e 1146     		mov	r1, r2
 754 03a0 1846     		mov	r0, r3
 755 03a2 FFF7FEFF 		bl	uart_send1
 756 03a6 0346     		mov	r3, r0
 757 03a8 002B     		cmp	r3, #0
 758 03aa 01D1     		bne	.L42
 180:srcc/uart.c   ****             return 0;  //·¢ËÍÊ§°Ü,·µ»Ø
 759              		.loc 2 180 0
 760 03ac 0023     		movs	r3, #0
 761 03ae 09E0     		b	.L40
 762              	.L42:
 177:srcc/uart.c   ****     {
 763              		.loc 2 177 0
 764 03b0 FB89     		ldrh	r3, [r7, #14]
 765 03b2 0133     		adds	r3, r3, #1
 766 03b4 FB81     		strh	r3, [r7, #14]	@ movhi
 767              	.L41:
 177:srcc/uart.c   ****     {
 768              		.loc 2 177 0 is_stmt 0
 769 03b6 FB89     		ldrh	r3, [r7, #14]
 770 03b8 BA68     		ldr	r2, [r7, #8]
 771 03ba 1344     		add	r3, r3, r2
 772 03bc 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 773 03be 002B     		cmp	r3, #0
 774 03c0 E8D1     		bne	.L43
 181:srcc/uart.c   ****     }
 182:srcc/uart.c   ****     return 1;          //·¢ËÍ³É¹¦
 775              		.loc 2 182 0 is_stmt 1
 776 03c2 0123     		movs	r3, #1
 777              	.L40:
 183:srcc/uart.c   **** }
 778              		.loc 2 183 0
 779 03c4 1846     		mov	r0, r3
 780 03c6 1037     		adds	r7, r7, #16
 781              		.cfi_def_cfa_offset 8
 782 03c8 BD46     		mov	sp, r7
 783              		.cfi_def_cfa_register 13
 784              		@ sp needed
 785 03ca 80BD     		pop	{r7, pc}
 786              		.cfi_endproc
 787              	.LFE126:
 789              		.align	1
 790              		.global	uart_re1
 791              		.syntax unified
 792              		.thumb
 793              		.thumb_func
 794              		.fpu fpv4-sp-d16
 796              	uart_re1:
 797              	.LFB127:
 184:srcc/uart.c   **** 
 185:srcc/uart.c   **** //======================================================================
 186:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_re1
 187:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 188:srcc/uart.c   **** //        *fp:½ÓÊÕ³É¹¦±êÖ¾µÄÖ¸Õë:*fp=1:½ÓÊÕ³É¹¦£»*fp=0:½ÓÊÕÊ§°Ü
 189:srcc/uart.c   **** //º¯Êý·µ»Ø£º½ÓÊÕ·µ»Ø×Ö½Ú
 190:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º´®ÐÐ½ÓÊÕ1¸ö×Ö½Ú
 191:srcc/uart.c   **** //======================================================================
 192:srcc/uart.c   **** uint8_t uart_re1(uint8_t uartNo,uint8_t *fp)
 193:srcc/uart.c   **** {
 798              		.loc 2 193 0
 799              		.cfi_startproc
 800              		@ args = 0, pretend = 0, frame = 24
 801              		@ frame_needed = 1, uses_anonymous_args = 0
 802 03cc 80B5     		push	{r7, lr}
 803              		.cfi_def_cfa_offset 8
 804              		.cfi_offset 7, -8
 805              		.cfi_offset 14, -4
 806 03ce 86B0     		sub	sp, sp, #24
 807              		.cfi_def_cfa_offset 32
 808 03d0 00AF     		add	r7, sp, #0
 809              		.cfi_def_cfa_register 7
 810 03d2 0346     		mov	r3, r0
 811 03d4 3960     		str	r1, [r7]
 812 03d6 FB71     		strb	r3, [r7, #7]
 194:srcc/uart.c   ****     uint32_t t;
 195:srcc/uart.c   ****     uint8_t  dat;			  //ÓÃÓÚ½ÓÊÕ·¢ËÍ»º³åÇøµÄÊý¾Ý
 196:srcc/uart.c   ****     EUSCI_A_Type* uartch;    //uartchÎªEUSCI_A_Type*ÀàÐÍÖ¸Õë
 197:srcc/uart.c   **** 	//ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 198:srcc/uart.c   **** 	if(!uart_is_uartNo(uartNo))
 813              		.loc 2 198 0
 814 03d8 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 815 03da 1846     		mov	r0, r3
 816 03dc FFF7FEFF 		bl	uart_is_uartNo
 817 03e0 0346     		mov	r3, r0
 818 03e2 002B     		cmp	r3, #0
 819 03e4 04D1     		bne	.L45
 199:srcc/uart.c   **** 	{
 200:srcc/uart.c   **** 		 *fp=0;
 820              		.loc 2 200 0
 821 03e6 3B68     		ldr	r3, [r7]
 822 03e8 0022     		movs	r2, #0
 823 03ea 1A70     		strb	r2, [r3]
 201:srcc/uart.c   **** 		 return 0;
 824              		.loc 2 201 0
 825 03ec 0023     		movs	r3, #0
 826 03ee 29E0     		b	.L46
 827              	.L45:
 202:srcc/uart.c   **** 	}
 203:srcc/uart.c   **** 	uartch=(EUSCI_A_Type*)UART_ARR[uartNo];
 828              		.loc 2 203 0
 829 03f0 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 830 03f2 164A     		ldr	r2, .L52
 831 03f4 52F82330 		ldr	r3, [r2, r3, lsl #2]
 832 03f8 FB60     		str	r3, [r7, #12]
 204:srcc/uart.c   **** 
 205:srcc/uart.c   **** 	for (t = 0; t < 0xFBBB; t++)//²éÑ¯Ö¸¶¨´ÎÊý
 833              		.loc 2 205 0
 834 03fa 0023     		movs	r3, #0
 835 03fc 7B61     		str	r3, [r7, #20]
 836 03fe 11E0     		b	.L47
 837              	.L50:
 206:srcc/uart.c   **** 	{
 207:srcc/uart.c   **** 		//ÅÐ¶Ï½ÓÊÕ»º³åÇøÊÇ·ñÂú
 208:srcc/uart.c   **** 		if(uartch->IFG & UCRXIFG)
 838              		.loc 2 208 0
 839 0400 FB68     		ldr	r3, [r7, #12]
 840 0402 9B8B     		ldrh	r3, [r3, #28]	@ movhi
 841 0404 9BB2     		uxth	r3, r3
 842 0406 03F00103 		and	r3, r3, #1
 843 040a 002B     		cmp	r3, #0
 844 040c 07D0     		beq	.L48
 209:srcc/uart.c   **** 		{
 210:srcc/uart.c   **** 			dat=uartch->RXBUF;//»ñÈ¡Êý¾Ý,Çå½ÓÊÕÖÐ¶ÏÎ»
 845              		.loc 2 210 0
 846 040e FB68     		ldr	r3, [r7, #12]
 847 0410 9B89     		ldrh	r3, [r3, #12]	@ movhi
 848 0412 9BB2     		uxth	r3, r3
 849 0414 FB74     		strb	r3, [r7, #19]
 211:srcc/uart.c   **** 			*fp=1;//½ÓÊÕ³É¹¦
 850              		.loc 2 211 0
 851 0416 3B68     		ldr	r3, [r7]
 852 0418 0122     		movs	r2, #1
 853 041a 1A70     		strb	r2, [r3]
 212:srcc/uart.c   **** 			break;
 854              		.loc 2 212 0
 855 041c 07E0     		b	.L49
 856              	.L48:
 205:srcc/uart.c   **** 	{
 857              		.loc 2 205 0
 858 041e 7B69     		ldr	r3, [r7, #20]
 859 0420 0133     		adds	r3, r3, #1
 860 0422 7B61     		str	r3, [r7, #20]
 861              	.L47:
 205:srcc/uart.c   **** 	{
 862              		.loc 2 205 0 is_stmt 0
 863 0424 7B69     		ldr	r3, [r7, #20]
 864 0426 4FF6BA32 		movw	r2, #64442
 865 042a 9342     		cmp	r3, r2
 866 042c E8D9     		bls	.L50
 867              	.L49:
 213:srcc/uart.c   **** 		}
 214:srcc/uart.c   **** 	}
 215:srcc/uart.c   **** 	//½áÊøÅÐ¶Ï
 216:srcc/uart.c   **** 	if(t >= 0xFBBB)
 868              		.loc 2 216 0 is_stmt 1
 869 042e 7B69     		ldr	r3, [r7, #20]
 870 0430 4FF6BA32 		movw	r2, #64442
 871 0434 9342     		cmp	r3, r2
 872 0436 04D9     		bls	.L51
 217:srcc/uart.c   **** 	{
 218:srcc/uart.c   **** 		 dat = 0xFF;
 873              		.loc 2 218 0
 874 0438 FF23     		movs	r3, #255
 875 043a FB74     		strb	r3, [r7, #19]
 219:srcc/uart.c   **** 		 *fp = 0;    //Î´ÊÕµ½Êý¾Ý
 876              		.loc 2 219 0
 877 043c 3B68     		ldr	r3, [r7]
 878 043e 0022     		movs	r2, #0
 879 0440 1A70     		strb	r2, [r3]
 880              	.L51:
 220:srcc/uart.c   **** 	}
 221:srcc/uart.c   **** 
 222:srcc/uart.c   ****     return dat;    //·µ»Ø½ÓÊÕµ½µÄÊý¾Ý
 881              		.loc 2 222 0
 882 0442 FB7C     		ldrb	r3, [r7, #19]	@ zero_extendqisi2
 883              	.L46:
 223:srcc/uart.c   **** }
 884              		.loc 2 223 0
 885 0444 1846     		mov	r0, r3
 886 0446 1837     		adds	r7, r7, #24
 887              		.cfi_def_cfa_offset 8
 888 0448 BD46     		mov	sp, r7
 889              		.cfi_def_cfa_register 13
 890              		@ sp needed
 891 044a 80BD     		pop	{r7, pc}
 892              	.L53:
 893              		.align	2
 894              	.L52:
 895 044c 00000000 		.word	UART_ARR
 896              		.cfi_endproc
 897              	.LFE127:
 899              		.align	1
 900              		.global	uart_reN
 901              		.syntax unified
 902              		.thumb
 903              		.thumb_func
 904              		.fpu fpv4-sp-d16
 906              	uart_reN:
 907              	.LFB128:
 224:srcc/uart.c   **** 
 225:srcc/uart.c   **** //======================================================================
 226:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_reN
 227:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 228:srcc/uart.c   **** //          buff: ½ÓÊÕ»º³åÇø
 229:srcc/uart.c   **** //          len:½ÓÊÕ³¤¶È
 230:srcc/uart.c   **** //º¯Êý·µ»Ø£ºº¯ÊýÖ´ÐÐ×´Ì¬ 1=½ÓÊÕ³É¹¦;0=½ÓÊÕÊ§°Ü
 231:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º´®ÐÐ ½ÓÊÕn¸ö×Ö½Ú,·ÅÈëbuffÖÐ
 232:srcc/uart.c   **** //======================================================================
 233:srcc/uart.c   **** uint8_t uart_reN(uint8_t uartNo ,uint16_t len ,uint8_t* buff)
 234:srcc/uart.c   **** {
 908              		.loc 2 234 0
 909              		.cfi_startproc
 910              		@ args = 0, pretend = 0, frame = 16
 911              		@ frame_needed = 1, uses_anonymous_args = 0
 912 0450 90B5     		push	{r4, r7, lr}
 913              		.cfi_def_cfa_offset 12
 914              		.cfi_offset 4, -12
 915              		.cfi_offset 7, -8
 916              		.cfi_offset 14, -4
 917 0452 85B0     		sub	sp, sp, #20
 918              		.cfi_def_cfa_offset 32
 919 0454 00AF     		add	r7, sp, #0
 920              		.cfi_def_cfa_register 7
 921 0456 0346     		mov	r3, r0
 922 0458 3A60     		str	r2, [r7]
 923 045a FB71     		strb	r3, [r7, #7]
 924 045c 0B46     		mov	r3, r1	@ movhi
 925 045e BB80     		strh	r3, [r7, #4]	@ movhi
 235:srcc/uart.c   ****     uint16_t i;
 236:srcc/uart.c   ****     uint8_t flag = 1;
 926              		.loc 2 236 0
 927 0460 0123     		movs	r3, #1
 928 0462 7B73     		strb	r3, [r7, #13]
 237:srcc/uart.c   ****     //ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 238:srcc/uart.c   **** 	 if(!uart_is_uartNo(uartNo))
 929              		.loc 2 238 0
 930 0464 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 931 0466 1846     		mov	r0, r3
 932 0468 FFF7FEFF 		bl	uart_is_uartNo
 933 046c 0346     		mov	r3, r0
 934 046e 002B     		cmp	r3, #0
 935 0470 01D1     		bne	.L55
 239:srcc/uart.c   **** 	 {
 240:srcc/uart.c   **** 	        return 0;
 936              		.loc 2 240 0
 937 0472 0023     		movs	r3, #0
 938 0474 1FE0     		b	.L61
 939              	.L55:
 241:srcc/uart.c   **** 	 }
 242:srcc/uart.c   ****     //ÅÐ¶ÏÊÇ·ñÄÜ½ÓÊÜÊý¾Ý
 243:srcc/uart.c   **** 	for (i = 0; i < len && flag==1; i++)
 940              		.loc 2 243 0
 941 0476 0023     		movs	r3, #0
 942 0478 FB81     		strh	r3, [r7, #14]	@ movhi
 943 047a 0EE0     		b	.L57
 944              	.L59:
 244:srcc/uart.c   **** 	{
 245:srcc/uart.c   **** 		buff[i] = uart_re1(uartNo, &flag); //½ÓÊÕÊý¾Ý
 945              		.loc 2 245 0
 946 047c FB89     		ldrh	r3, [r7, #14]
 947 047e 3A68     		ldr	r2, [r7]
 948 0480 D418     		adds	r4, r2, r3
 949 0482 07F10D02 		add	r2, r7, #13
 950 0486 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 951 0488 1146     		mov	r1, r2
 952 048a 1846     		mov	r0, r3
 953 048c FFF7FEFF 		bl	uart_re1
 954 0490 0346     		mov	r3, r0
 955 0492 2370     		strb	r3, [r4]
 243:srcc/uart.c   **** 	{
 956              		.loc 2 243 0
 957 0494 FB89     		ldrh	r3, [r7, #14]
 958 0496 0133     		adds	r3, r3, #1
 959 0498 FB81     		strh	r3, [r7, #14]	@ movhi
 960              	.L57:
 243:srcc/uart.c   **** 	{
 961              		.loc 2 243 0 is_stmt 0
 962 049a FA89     		ldrh	r2, [r7, #14]
 963 049c BB88     		ldrh	r3, [r7, #4]
 964 049e 9A42     		cmp	r2, r3
 965 04a0 02D2     		bcs	.L58
 243:srcc/uart.c   **** 	{
 966              		.loc 2 243 0
 967 04a2 7B7B     		ldrb	r3, [r7, #13]	@ zero_extendqisi2
 968 04a4 012B     		cmp	r3, #1
 969 04a6 E9D0     		beq	.L59
 970              	.L58:
 246:srcc/uart.c   **** 	}
 247:srcc/uart.c   **** 	if (i < len)
 971              		.loc 2 247 0 is_stmt 1
 972 04a8 FA89     		ldrh	r2, [r7, #14]
 973 04aa BB88     		ldrh	r3, [r7, #4]
 974 04ac 9A42     		cmp	r2, r3
 975 04ae 01D2     		bcs	.L60
 248:srcc/uart.c   **** 		return 0; //½ÓÊÕÊ§°Ü
 976              		.loc 2 248 0
 977 04b0 0023     		movs	r3, #0
 978 04b2 00E0     		b	.L61
 979              	.L60:
 249:srcc/uart.c   **** 	else
 250:srcc/uart.c   **** 		return 1; //½ÓÊÕ³É¹¦
 980              		.loc 2 250 0
 981 04b4 0123     		movs	r3, #1
 982              	.L61:
 251:srcc/uart.c   **** }
 983              		.loc 2 251 0
 984 04b6 1846     		mov	r0, r3
 985 04b8 1437     		adds	r7, r7, #20
 986              		.cfi_def_cfa_offset 12
 987 04ba BD46     		mov	sp, r7
 988              		.cfi_def_cfa_register 13
 989              		@ sp needed
 990 04bc 90BD     		pop	{r4, r7, pc}
 991              		.cfi_endproc
 992              	.LFE128:
 994              		.align	1
 995              		.global	uart_enable_re_int
 996              		.syntax unified
 997              		.thumb
 998              		.thumb_func
 999              		.fpu fpv4-sp-d16
 1001              	uart_enable_re_int:
 1002              	.LFB129:
 252:srcc/uart.c   **** 
 253:srcc/uart.c   **** //======================================================================
 254:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_enable_re_int
 255:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 256:srcc/uart.c   **** //º¯Êý·µ»Ø£ºÎÞ
 257:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º¿ª´®¿Ú½ÓÊÕÖÐ¶Ï
 258:srcc/uart.c   **** //======================================================================
 259:srcc/uart.c   **** void uart_enable_re_int(uint8_t uartNo)
 260:srcc/uart.c   **** {
 1003              		.loc 2 260 0
 1004              		.cfi_startproc
 1005              		@ args = 0, pretend = 0, frame = 16
 1006              		@ frame_needed = 1, uses_anonymous_args = 0
 1007 04be 80B5     		push	{r7, lr}
 1008              		.cfi_def_cfa_offset 8
 1009              		.cfi_offset 7, -8
 1010              		.cfi_offset 14, -4
 1011 04c0 84B0     		sub	sp, sp, #16
 1012              		.cfi_def_cfa_offset 24
 1013 04c2 00AF     		add	r7, sp, #0
 1014              		.cfi_def_cfa_register 7
 1015 04c4 0346     		mov	r3, r0
 1016 04c6 FB71     		strb	r3, [r7, #7]
 261:srcc/uart.c   **** 	EUSCI_A_Type* uartch;
 262:srcc/uart.c   **** 	//ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 263:srcc/uart.c   **** 	 if(!uart_is_uartNo(uartNo))
 1017              		.loc 2 263 0
 1018 04c8 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1019 04ca 1846     		mov	r0, r3
 1020 04cc FFF7FEFF 		bl	uart_is_uartNo
 1021 04d0 0346     		mov	r3, r0
 1022 04d2 002B     		cmp	r3, #0
 1023 04d4 13D0     		beq	.L65
 264:srcc/uart.c   **** 	 {
 265:srcc/uart.c   **** 			return ;
 266:srcc/uart.c   **** 	 }
 267:srcc/uart.c   **** 	 uartch= (EUSCI_A_Type*)UART_ARR[uartNo];//»ñÈ¡UART»ùµØÖ·
 1024              		.loc 2 267 0
 1025 04d6 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1026 04d8 0B4A     		ldr	r2, .L66
 1027 04da 52F82330 		ldr	r3, [r2, r3, lsl #2]
 1028 04de FB60     		str	r3, [r7, #12]
 268:srcc/uart.c   **** 	 uartch->IE|=UCRXIE;//´ò¿ªUART½ÓÊÕÖÐ¶Ï
 1029              		.loc 2 268 0
 1030 04e0 FB68     		ldr	r3, [r7, #12]
 1031 04e2 5B8B     		ldrh	r3, [r3, #26]	@ movhi
 1032 04e4 9BB2     		uxth	r3, r3
 1033 04e6 43F00103 		orr	r3, r3, #1
 1034 04ea 9AB2     		uxth	r2, r3
 1035 04ec FB68     		ldr	r3, [r7, #12]
 1036 04ee 5A83     		strh	r2, [r3, #26]	@ movhi
 269:srcc/uart.c   ****      NVIC_EnableIRQ(table_irq_uart[uartNo]);//ÔÚNVICÄ£¿éÖÐÊ¹ÄÜEUSCIAxÖÐ¶Ï
 1037              		.loc 2 269 0
 1038 04f0 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1039 04f2 064A     		ldr	r2, .L66+4
 1040 04f4 D356     		ldrsb	r3, [r2, r3]
 1041 04f6 1846     		mov	r0, r3
 1042 04f8 FFF782FD 		bl	NVIC_EnableIRQ
 1043 04fc 00E0     		b	.L62
 1044              	.L65:
 265:srcc/uart.c   **** 	 }
 1045              		.loc 2 265 0
 1046 04fe 00BF     		nop
 1047              	.L62:
 270:srcc/uart.c   **** 
 271:srcc/uart.c   **** }
 1048              		.loc 2 271 0
 1049 0500 1037     		adds	r7, r7, #16
 1050              		.cfi_def_cfa_offset 8
 1051 0502 BD46     		mov	sp, r7
 1052              		.cfi_def_cfa_register 13
 1053              		@ sp needed
 1054 0504 80BD     		pop	{r7, pc}
 1055              	.L67:
 1056 0506 00BF     		.align	2
 1057              	.L66:
 1058 0508 00000000 		.word	UART_ARR
 1059 050c 00000000 		.word	table_irq_uart
 1060              		.cfi_endproc
 1061              	.LFE129:
 1063              		.align	1
 1064              		.global	uart_disable_re_int
 1065              		.syntax unified
 1066              		.thumb
 1067              		.thumb_func
 1068              		.fpu fpv4-sp-d16
 1070              	uart_disable_re_int:
 1071              	.LFB130:
 272:srcc/uart.c   **** 
 273:srcc/uart.c   **** //======================================================================
 274:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_disable_re_int
 275:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 276:srcc/uart.c   **** //º¯Êý·µ»Ø£ºÎÞ
 277:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º¹Ø´®¿Ú½ÓÊÕÖÐ¶Ï
 278:srcc/uart.c   **** //======================================================================
 279:srcc/uart.c   **** void uart_disable_re_int(uint8_t uartNo)
 280:srcc/uart.c   **** {
 1072              		.loc 2 280 0
 1073              		.cfi_startproc
 1074              		@ args = 0, pretend = 0, frame = 16
 1075              		@ frame_needed = 1, uses_anonymous_args = 0
 1076 0510 80B5     		push	{r7, lr}
 1077              		.cfi_def_cfa_offset 8
 1078              		.cfi_offset 7, -8
 1079              		.cfi_offset 14, -4
 1080 0512 84B0     		sub	sp, sp, #16
 1081              		.cfi_def_cfa_offset 24
 1082 0514 00AF     		add	r7, sp, #0
 1083              		.cfi_def_cfa_register 7
 1084 0516 0346     		mov	r3, r0
 1085 0518 FB71     		strb	r3, [r7, #7]
 281:srcc/uart.c   **** 
 282:srcc/uart.c   **** 	 EUSCI_A_Type* uartch;
 283:srcc/uart.c   **** 	//ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 284:srcc/uart.c   **** 	 if(!uart_is_uartNo(uartNo))
 1086              		.loc 2 284 0
 1087 051a FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1088 051c 1846     		mov	r0, r3
 1089 051e FFF7FEFF 		bl	uart_is_uartNo
 1090 0522 0346     		mov	r3, r0
 1091 0524 002B     		cmp	r3, #0
 1092 0526 13D0     		beq	.L71
 285:srcc/uart.c   **** 	 {
 286:srcc/uart.c   **** 			return ;
 287:srcc/uart.c   **** 	 }
 288:srcc/uart.c   **** 	 uartch=(EUSCI_A_Type*) UART_ARR[uartNo];//»ñÈ¡UART»ùµØÖ·
 1093              		.loc 2 288 0
 1094 0528 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1095 052a 0B4A     		ldr	r2, .L72
 1096 052c 52F82330 		ldr	r3, [r2, r3, lsl #2]
 1097 0530 FB60     		str	r3, [r7, #12]
 289:srcc/uart.c   **** 	 uartch->IE&=~UCRXIE;//½ûÖ¹UART½ÓÊÕÖÐ¶Ï
 1098              		.loc 2 289 0
 1099 0532 FB68     		ldr	r3, [r7, #12]
 1100 0534 5B8B     		ldrh	r3, [r3, #26]	@ movhi
 1101 0536 9BB2     		uxth	r3, r3
 1102 0538 23F00103 		bic	r3, r3, #1
 1103 053c 9AB2     		uxth	r2, r3
 1104 053e FB68     		ldr	r3, [r7, #12]
 1105 0540 5A83     		strh	r2, [r3, #26]	@ movhi
 290:srcc/uart.c   ****      NVIC_DisableIRQ(table_irq_uart[uartNo]);//ÔÚNVICÄ£¿éÖÐÊ¹ÄÜEUSCIAxÖÐ¶Ï
 1106              		.loc 2 290 0
 1107 0542 FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1108 0544 054A     		ldr	r2, .L72+4
 1109 0546 D356     		ldrsb	r3, [r2, r3]
 1110 0548 1846     		mov	r0, r3
 1111 054a FFF773FD 		bl	NVIC_DisableIRQ
 1112 054e 00E0     		b	.L68
 1113              	.L71:
 286:srcc/uart.c   **** 	 }
 1114              		.loc 2 286 0
 1115 0550 00BF     		nop
 1116              	.L68:
 291:srcc/uart.c   **** 
 292:srcc/uart.c   **** }
 1117              		.loc 2 292 0
 1118 0552 1037     		adds	r7, r7, #16
 1119              		.cfi_def_cfa_offset 8
 1120 0554 BD46     		mov	sp, r7
 1121              		.cfi_def_cfa_register 13
 1122              		@ sp needed
 1123 0556 80BD     		pop	{r7, pc}
 1124              	.L73:
 1125              		.align	2
 1126              	.L72:
 1127 0558 00000000 		.word	UART_ARR
 1128 055c 00000000 		.word	table_irq_uart
 1129              		.cfi_endproc
 1130              	.LFE130:
 1132              		.align	1
 1133              		.global	uart_get_re_int
 1134              		.syntax unified
 1135              		.thumb
 1136              		.thumb_func
 1137              		.fpu fpv4-sp-d16
 1139              	uart_get_re_int:
 1140              	.LFB131:
 293:srcc/uart.c   **** 
 294:srcc/uart.c   **** //======================================================================
 295:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_get_re_int
 296:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 297:srcc/uart.c   **** //º¯Êý·µ»Ø£º½ÓÊÕÖÐ¶Ï±êÖ¾ 1=ÓÐ½ÓÊÕÖÐ¶Ï;0=ÎÞ½ÓÊÕÖÐ¶Ï
 298:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£º»ñÈ¡´®¿Ú½ÓÊÕÖÐ¶Ï±êÖ¾,Í¬Ê±½ûÓÃ·¢ËÍÖÐ¶Ï
 299:srcc/uart.c   **** //======================================================================
 300:srcc/uart.c   **** uint8_t uart_get_re_int(uint8_t uartNo)
 301:srcc/uart.c   **** {
 1141              		.loc 2 301 0
 1142              		.cfi_startproc
 1143              		@ args = 0, pretend = 0, frame = 16
 1144              		@ frame_needed = 1, uses_anonymous_args = 0
 1145 0560 80B5     		push	{r7, lr}
 1146              		.cfi_def_cfa_offset 8
 1147              		.cfi_offset 7, -8
 1148              		.cfi_offset 14, -4
 1149 0562 84B0     		sub	sp, sp, #16
 1150              		.cfi_def_cfa_offset 24
 1151 0564 00AF     		add	r7, sp, #0
 1152              		.cfi_def_cfa_register 7
 1153 0566 0346     		mov	r3, r0
 1154 0568 FB71     		strb	r3, [r7, #7]
 302:srcc/uart.c   ****     //uint8_t flag;
 303:srcc/uart.c   ****     EUSCI_A_Type* uartch;
 304:srcc/uart.c   ****     //ÅÐ¶Ï´«Èë´®¿ÚºÅ²ÎÊýÊÇ·ñÓÐÎó£¬ÓÐÎóÖ±½ÓÍË³ö
 305:srcc/uart.c   **** 	 if(!uart_is_uartNo(uartNo))
 1155              		.loc 2 305 0
 1156 056a FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1157 056c 1846     		mov	r0, r3
 1158 056e FFF7FEFF 		bl	uart_is_uartNo
 1159 0572 0346     		mov	r3, r0
 1160 0574 002B     		cmp	r3, #0
 1161 0576 01D1     		bne	.L75
 306:srcc/uart.c   **** 	 {
 307:srcc/uart.c   **** 			return 0;
 1162              		.loc 2 307 0
 1163 0578 0023     		movs	r3, #0
 1164 057a 13E0     		b	.L76
 1165              	.L75:
 308:srcc/uart.c   **** 	 }
 309:srcc/uart.c   **** 	 uartch= (EUSCI_A_Type*)UART_ARR[uartNo];//»ñÈ¡UART»ùµØÖ·
 1166              		.loc 2 309 0
 1167 057c FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1168 057e 0B4A     		ldr	r2, .L77
 1169 0580 52F82330 		ldr	r3, [r2, r3, lsl #2]
 1170 0584 FB60     		str	r3, [r7, #12]
 310:srcc/uart.c   **** 	 uartch->IE&=~UCTXIE;//½ûÓÃ´®¿Ú·¢ËÍÖÐ¶Ï£¬·ÀÖ¹ÎóÖÐ¶Ï
 1171              		.loc 2 310 0
 1172 0586 FB68     		ldr	r3, [r7, #12]
 1173 0588 5B8B     		ldrh	r3, [r3, #26]	@ movhi
 1174 058a 9BB2     		uxth	r3, r3
 1175 058c 23F00203 		bic	r3, r3, #2
 1176 0590 9AB2     		uxth	r2, r3
 1177 0592 FB68     		ldr	r3, [r7, #12]
 1178 0594 5A83     		strh	r2, [r3, #26]	@ movhi
 311:srcc/uart.c   **** 	 //»ñÈ¡½ÓÊÕÖÐ¶Ï±êÖ¾£¬ÐèÅÐ¶ÏRIE;
 312:srcc/uart.c   **** 	 return BGET(UCRXIE_OFS,uartch->IE);
 1179              		.loc 2 312 0
 1180 0596 FB68     		ldr	r3, [r7, #12]
 1181 0598 5B8B     		ldrh	r3, [r3, #26]	@ movhi
 1182 059a 9BB2     		uxth	r3, r3
 1183 059c DBB2     		uxtb	r3, r3
 1184 059e 03F00103 		and	r3, r3, #1
 1185 05a2 DBB2     		uxtb	r3, r3
 1186              	.L76:
 313:srcc/uart.c   **** }
 1187              		.loc 2 313 0
 1188 05a4 1846     		mov	r0, r3
 1189 05a6 1037     		adds	r7, r7, #16
 1190              		.cfi_def_cfa_offset 8
 1191 05a8 BD46     		mov	sp, r7
 1192              		.cfi_def_cfa_register 13
 1193              		@ sp needed
 1194 05aa 80BD     		pop	{r7, pc}
 1195              	.L78:
 1196              		.align	2
 1197              	.L77:
 1198 05ac 00000000 		.word	UART_ARR
 1199              		.cfi_endproc
 1200              	.LFE131:
 1202              		.align	1
 1203              		.global	uart_is_uartNo
 1204              		.syntax unified
 1205              		.thumb
 1206              		.thumb_func
 1207              		.fpu fpv4-sp-d16
 1209              	uart_is_uartNo:
 1210              	.LFB132:
 314:srcc/uart.c   **** 
 315:srcc/uart.c   **** //----------------------ÒÔÏÂÎªÄÚ²¿º¯Êý´æ·Å´¦--------------------------------------
 316:srcc/uart.c   **** //=====================================================================
 317:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºuart_is_uartNo
 318:srcc/uart.c   **** //º¯Êý·µ»Ø£º1:´®¿ÚºÅÔÚºÏÀí·¶Î§ÄÚ£¬0£º´®¿ÚºÅ²»ºÏÀí
 319:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºuartNo:´®¿ÚºÅ£ºUART_0¡¢UART_1¡¢UART_2¡¢UART_3
 320:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£ºÎª³ÌÐò½¡×³ÐÔ¶øÅÐ¶ÏuartNoÊÇ·ñÔÚ´®¿ÚÊý×Ö·¶Î§ÄÚ
 321:srcc/uart.c   **** //=====================================================================
 322:srcc/uart.c   **** uint8_t uart_is_uartNo(uint8_t uartNo)
 323:srcc/uart.c   **** {
 1211              		.loc 2 323 0
 1212              		.cfi_startproc
 1213              		@ args = 0, pretend = 0, frame = 8
 1214              		@ frame_needed = 1, uses_anonymous_args = 0
 1215              		@ link register save eliminated.
 1216 05b0 80B4     		push	{r7}
 1217              		.cfi_def_cfa_offset 4
 1218              		.cfi_offset 7, -4
 1219 05b2 83B0     		sub	sp, sp, #12
 1220              		.cfi_def_cfa_offset 16
 1221 05b4 00AF     		add	r7, sp, #0
 1222              		.cfi_def_cfa_register 7
 1223 05b6 0346     		mov	r3, r0
 1224 05b8 FB71     		strb	r3, [r7, #7]
 324:srcc/uart.c   ****     if(((int)uartNo < (int)UART_0 || (int)uartNo >(int)UART_3))
 1225              		.loc 2 324 0
 1226 05ba FB79     		ldrb	r3, [r7, #7]	@ zero_extendqisi2
 1227 05bc 032B     		cmp	r3, #3
 1228 05be 01D9     		bls	.L80
 325:srcc/uart.c   ****         return 0;
 1229              		.loc 2 325 0
 1230 05c0 0023     		movs	r3, #0
 1231 05c2 00E0     		b	.L81
 1232              	.L80:
 326:srcc/uart.c   ****     else
 327:srcc/uart.c   ****         return 1;
 1233              		.loc 2 327 0
 1234 05c4 0123     		movs	r3, #1
 1235              	.L81:
 328:srcc/uart.c   **** }
 1236              		.loc 2 328 0
 1237 05c6 1846     		mov	r0, r3
 1238 05c8 0C37     		adds	r7, r7, #12
 1239              		.cfi_def_cfa_offset 4
 1240 05ca BD46     		mov	sp, r7
 1241              		.cfi_def_cfa_register 13
 1242              		@ sp needed
 1243 05cc 5DF8047B 		ldr	r7, [sp], #4
 1244              		.cfi_restore 7
 1245              		.cfi_def_cfa_offset 0
 1246 05d0 7047     		bx	lr
 1247              		.cfi_endproc
 1248              	.LFE132:
 1250              		.align	1
 1251              		.global	BRSxSel
 1252              		.syntax unified
 1253              		.thumb
 1254              		.thumb_func
 1255              		.fpu fpv4-sp-d16
 1257              	BRSxSel:
 1258              	.LFB133:
 329:srcc/uart.c   **** 
 330:srcc/uart.c   **** 
 331:srcc/uart.c   **** //======================================================================
 332:srcc/uart.c   **** //º¯ÊýÃû³Æ£ºBRSxSel
 333:srcc/uart.c   **** //²ÎÊýËµÃ÷£ºfra:²¨ÌØÂÊ¼ÆËãµÄÐ¡Êý²¿·Ö£¬fra=1.0*fBRCLK/(16*baud_rate)µÄÐ¡Êý²¿·Ö
 334:srcc/uart.c   **** //º¯Êý·µ»Ø£ºÊý×éValBRSxS[]ÖÐÓëfraÏÂ±êÒ»ÖÂµÄ8Î»ÊýÖµ
 335:srcc/uart.c   **** //¹¦ÄÜ¸ÅÒª£ºÓÃ²¨ÌØÂÊ¼ÆËãµÄÐ¡Êý²¿·ÖÕÒ³ö¶¨ÒåµÄUCBRFxµÄ¶ÔÓ¦¸³Öµ
 336:srcc/uart.c   **** //======================================================================
 337:srcc/uart.c   **** uint8_t BRSxSel(double fra)
 338:srcc/uart.c   **** {
 1259              		.loc 2 338 0
 1260              		.cfi_startproc
 1261              		@ args = 0, pretend = 0, frame = 16
 1262              		@ frame_needed = 1, uses_anonymous_args = 0
 1263 05d2 90B5     		push	{r4, r7, lr}
 1264              		.cfi_def_cfa_offset 12
 1265              		.cfi_offset 4, -12
 1266              		.cfi_offset 7, -8
 1267              		.cfi_offset 14, -4
 1268 05d4 85B0     		sub	sp, sp, #20
 1269              		.cfi_def_cfa_offset 32
 1270 05d6 00AF     		add	r7, sp, #0
 1271              		.cfi_def_cfa_register 7
 1272 05d8 87ED000B 		vstr.64	d0, [r7]
 339:srcc/uart.c   **** 	uint8_t brs;
 340:srcc/uart.c   **** 	uint16_t i,temp;
 341:srcc/uart.c   **** 	brs=0;
 1273              		.loc 2 341 0
 1274 05dc 0023     		movs	r3, #0
 1275 05de FB73     		strb	r3, [r7, #15]
 342:srcc/uart.c   **** 	temp=(uint16_t)(fra*1000);
 1276              		.loc 2 342 0
 1277 05e0 4FF00002 		mov	r2, #0
 1278 05e4 134B     		ldr	r3, .L88
 1279 05e6 D7E90001 		ldrd	r0, [r7]
 1280 05ea FFF7FEFF 		bl	__aeabi_dmul
 1281              	.LVL8:
 1282 05ee 0346     		mov	r3, r0
 1283 05f0 0C46     		mov	r4, r1
 1284 05f2 1846     		mov	r0, r3
 1285 05f4 2146     		mov	r1, r4
 1286 05f6 FFF7FEFF 		bl	__aeabi_d2uiz
 1287              	.LVL9:
 1288 05fa 0346     		mov	r3, r0
 1289 05fc 7B81     		strh	r3, [r7, #10]	@ movhi
 343:srcc/uart.c   **** 	for(i=0;i<36;i++)
 1290              		.loc 2 343 0
 1291 05fe 0023     		movs	r3, #0
 1292 0600 BB81     		strh	r3, [r7, #12]	@ movhi
 1293 0602 0EE0     		b	.L83
 1294              	.L86:
 344:srcc/uart.c   **** 	{
 345:srcc/uart.c   **** 		if(BRSxS[i]==temp)
 1295              		.loc 2 345 0
 1296 0604 BB89     		ldrh	r3, [r7, #12]
 1297 0606 0C4A     		ldr	r2, .L88+4
 1298 0608 32F81330 		ldrh	r3, [r2, r3, lsl #1]
 1299 060c 7A89     		ldrh	r2, [r7, #10]
 1300 060e 9A42     		cmp	r2, r3
 1301 0610 04D1     		bne	.L84
 346:srcc/uart.c   **** 		{
 347:srcc/uart.c   **** 			brs=ValBRSxS[i];
 1302              		.loc 2 347 0
 1303 0612 BB89     		ldrh	r3, [r7, #12]
 1304 0614 094A     		ldr	r2, .L88+8
 1305 0616 D35C     		ldrb	r3, [r2, r3]
 1306 0618 FB73     		strb	r3, [r7, #15]
 348:srcc/uart.c   **** 			break;
 1307              		.loc 2 348 0
 1308 061a 05E0     		b	.L85
 1309              	.L84:
 343:srcc/uart.c   **** 	{
 1310              		.loc 2 343 0
 1311 061c BB89     		ldrh	r3, [r7, #12]
 1312 061e 0133     		adds	r3, r3, #1
 1313 0620 BB81     		strh	r3, [r7, #12]	@ movhi
 1314              	.L83:
 343:srcc/uart.c   **** 	{
 1315              		.loc 2 343 0 is_stmt 0
 1316 0622 BB89     		ldrh	r3, [r7, #12]
 1317 0624 232B     		cmp	r3, #35
 1318 0626 EDD9     		bls	.L86
 1319              	.L85:
 349:srcc/uart.c   **** 		}
 350:srcc/uart.c   **** 	}
 351:srcc/uart.c   **** 	return brs;
 1320              		.loc 2 351 0 is_stmt 1
 1321 0628 FB7B     		ldrb	r3, [r7, #15]	@ zero_extendqisi2
 352:srcc/uart.c   **** }
 1322              		.loc 2 352 0
 1323 062a 1846     		mov	r0, r3
 1324 062c 1437     		adds	r7, r7, #20
 1325              		.cfi_def_cfa_offset 12
 1326 062e BD46     		mov	sp, r7
 1327              		.cfi_def_cfa_register 13
 1328              		@ sp needed
 1329 0630 90BD     		pop	{r4, r7, pc}
 1330              	.L89:
 1331 0632 00BF     		.align	2
 1332              	.L88:
 1333 0634 00408F40 		.word	1083129856
 1334 0638 00000000 		.word	BRSxS
 1335 063c 00000000 		.word	ValBRSxS
 1336              		.cfi_endproc
 1337              	.LFE133:
 1339              	.Letext0:
 1340              		.file 3 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 1341              		.file 4 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 1342              		.file 5 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH04-GPIO\\
 1343              		.file 6 "C:\\Users\\lenovo\\Desktop\\MSP-20210417\\MSP-20210417\\User-MSP432-20210417\\CH04-GPIO\\
 1344              		.file 7 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\lock.h"
 1345              		.file 8 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\_types.h"
 1346              		.file 9 "d:\\ahl-gec-ide(4.20)\\gcc\\lib\\gcc\\arm-none-eabi\\7.2.1\\include\\stddef.h"
 1347              		.file 10 "d:\\ahl-gec-ide(4.20)\\gcc\\arm-none-eabi\\include\\sys\\reent.h"
DEFINED SYMBOLS
                            *ABS*:00000000 uart.c
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:17     .text:00000000 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:23     .text:00000000 NVIC_EnableIRQ
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:63     .text:00000030 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:67     .text:00000034 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:73     .text:00000034 NVIC_DisableIRQ
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:113    .text:00000064 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:118    .data:00000000 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:121    .data:00000000 UART_ARR
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:127    .rodata:00000000 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:130    .rodata:00000000 table_irq_uart
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:140    .data:00000010 BRSxS
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:181    .data:00000058 ValBRSxS
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:225    .text:00000068 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:232    .text:00000068 uart_init
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1209   .text:000005b0 uart_is_uartNo
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:285    .text:000000b4 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:289    .text:000000c4 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1257   .text:000005d2 BRSxSel
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:492    .text:00000250 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:509    .text:00000288 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:516    .text:00000288 uart_send1
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:605    .text:000002fc $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:609    .text:00000300 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:616    .text:00000300 uart_sendN
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:708    .text:00000368 uart_send_string
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:796    .text:000003cc uart_re1
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:895    .text:0000044c $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:899    .text:00000450 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:906    .text:00000450 uart_reN
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1001   .text:000004be uart_enable_re_int
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1058   .text:00000508 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1063   .text:00000510 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1070   .text:00000510 uart_disable_re_int
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1127   .text:00000558 $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1132   .text:00000560 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1139   .text:00000560 uart_get_re_int
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1198   .text:000005ac $d
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1202   .text:000005b0 $t
C:\Users\lenovo\AppData\Local\Temp\ccFt6Dlx.s:1333   .text:00000634 $d

UNDEFINED SYMBOLS
__aeabi_ui2d
__aeabi_ddiv
__aeabi_d2uiz
__aeabi_i2d
__aeabi_dsub
__aeabi_dmul
